Electronic Components Datasheet Search
  English  ▼

Delete All


Preview PDF Download HTML

DM74LS193 Datasheet(PDF) 1 Page - Fairchild Semiconductor

Part No. DM74LS193
Description  Synchronous 4-Bit Binary Counter with Dual Clock
Download  7 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

DM74LS193 Datasheet(HTML) 1 Page - Fairchild Semiconductor

  DM74LS193 Datasheet HTML 1Page - Fairchild Semiconductor DM74LS193 Datasheet HTML 2Page - Fairchild Semiconductor DM74LS193 Datasheet HTML 3Page - Fairchild Semiconductor DM74LS193 Datasheet HTML 4Page - Fairchild Semiconductor DM74LS193 Datasheet HTML 5Page - Fairchild Semiconductor DM74LS193 Datasheet HTML 6Page - Fairchild Semiconductor DM74LS193 Datasheet HTML 7Page - Fairchild Semiconductor  
Zoom Inzoom in Zoom Outzoom out
 1 / 7 page
background image
© 2000 Fairchild Semiconductor Corporation
September 1986
Revised March 2000
Synchronous 4-Bit Binary Counter with Dual Clock
General Description
The DM74LS193 circuit is a synchronous up/down 4-bit
binary counter. Synchronous operation is provided by hav-
ing all flip-flops clocked simultaneously, so that the outputs
change together when so instructed by the steering logic.
This mode of operation eliminates the output counting
spikes normally associated with asynchronous (ripple-
clock) counters.
The outputs of the four master-slave flip-flops are triggered
by a LOW-to-HIGH level transition of either count (clock)
input. The direction of counting is determined by which
count input is pulsed while the other count input is held
The counter is fully programmable; that is, each output may
be preset to either level by entering the desired data at the
inputs while the load input is LOW. The output will change
independently of the count pulses. This feature allows the
counters to be used as modulo-N dividers by simply modi-
fying the count length with the preset inputs.
A clear input has been provided which, when taken to a
high level, forces all outputs to the low level; independent
of the count and load inputs. The clear, count, and load
inputs are buffered to lower the drive requirements of clock
drivers, etc., required for long words.
These counters were designed to be cascaded without the
need for external circuitry. Both borrow and carry outputs
are available to cascade both the up and down counting
functions. The borrow output produces a pulse equal in
width to the count down input when the counter underflows.
Similarly, the carry output produces a pulse equal in width
to the count down input when an overflow condition exists.
The counters can then be easily cascaded by feeding the
borrow and carry outputs to the count down and count up
inputs respectively of the succeeding counter.
s Fully independent clear input
s Synchronous operation
s Cascading circuitry provided internally
s Individual preset each flip-flop
Ordering Code:
Connection Diagram
Order Number
Package Number
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Html Pages

1  2  3  4  5  6  7 

Datasheet Download

Go To PDF Page

Link URL

Privacy Policy
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com

Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn