DM74LS169A datasheet(1/8 Pages) FAIRCHILD | Synchronous 4-Bit Up/Down Binary Counter

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DM74LS169A

Synchronous 4-Bit Up/Down Binary Counter

General Description

This synchronous presettable counter features an internal

carry look-ahead for cascading in high-speed counting appli-

cations. Synchronous operation is provided by having all

flip-flops clocked simultaneously, so that the outputs all

change at the same time when so instructed by the

count-enable inputs and internal gating. This mode of opera-

tion helps eliminate the output counting spikes that are nor-

mally associated with asynchronous (ripple clock) counters.

A buffered clock input triggers the four master-slave flip-flops

on the rising edge of the clock waveform.

This counter is fully programmable; that is, the outputs may

each be preset either high or low. The load input circuitry al-

lows loading with the carry-enable output of cascaded

counters. As loading is synchronous, setting up a low level at

the load input disables the counter and causes the outputs to

agree with the data inputs after the next clock pulse.

The carry look-ahead circuitry permits cascading counters

for n-bit synchronous applications without additional gating.

Both count-enable inputs (P and T) must be low to count.

The direction of the count is determined by the level of the

up/down input. When the input is high, the counter counts

up; when low, it counts down. Input T is fed forward to enable

the carry outputs. The carry output thus enabled will produce

a low-level output pulse with a duration approximately equal

to the high portion of the Q

A output when counting up, and

approximately equal to the low portion of the Q

A output when

counting down. This low-level overflow carry pulse can be

used to enable successively cascaded stages. Transitions at

the enable P or T inputs are allowed regardless of the level

of the clock input. All inputs are diode clamped to minimize

transmission-line effects, thereby simplifying system design.

This counter features a fully independent clock circuit.

Changes at control inputs (enable P, enable T, load, up/

down), which modify the operating mode, have no effect until

clocking occurs. The function of the counter (whether en-

abled, disabled, loading, or counting) will be dictated solely

by the conditions meeting the stable setup and hold times.

Features

Fully synchronous operation for counting and

programming.

Internal look-ahead for fast counting.

Carry output for n-bit cascading.

Fully independent clock circuit

Connection Diagram

Dual-In-Line Package

DS006401-1

Order Number 54LS169DMQB, 54LS169FMQB, 54LS169LMQB,

DM54LS169AJ, DM54LS169AW, DM74LS169AM or DM74LS169AN

See Package Number E20A, J16A, M16A, N16E or W16A

April 1998

DS006401

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