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MAX14920 Datasheet(PDF) 5 Page - Maxim Integrated Products |
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MAX14920 Datasheet(HTML) 5 Page - Maxim Integrated Products |
5 / 29 page 5 Maxim Integrated MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs DC ELECTRICAL CHARACTERISTICS (continued) (VP = +65V, DGND = AGND, VL = VEN = +3.3V, VA = +5V, CSAMPLE = 1FF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) Note 2: All devices are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. Note 3: Where n = 1–12 (MAX14920) and n = 1–16 (MAX14921). Note 4: Output error VO_ERR is the difference between the input cell difference voltage (VD = VCV(n) - VCV(n - 1)) and the output voltage VAOUT. Where n = 1–12 (MAX14920) and n = 1–16 (MAX14921). Output error depends on buffer ampli- fier errors and parasitic capacitance charge injection error. Since parasitic capacitance error is PCB dependent, output error is guaranteed by design for a sampling capacitor of 1FF and parasitic capacitance less than 2.5pF on CTn (see the Measurement Accuracy section for a detailed explanation). Note 5: Buffer amplifier self-calibrates its offset at power-up and every time it is requested. Due to possible thermal drift after power-up phase, it is suggested to run self-calibration on a regular basis to get best performance (see the Buffer Amplifier Offset Calibration section for a detailed explanation). Note 6: Amplifier error is the sum of all errors including amplifier offset and gain error. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Level-Shifting Delay Time tLS_DELAY Delay from SMPLB set to 1 or SAMPL falling edge to shifting of all cell voltages to ground and available for reading 25 50 F s AOUT Voltage-Droop Time tDROOP Droop to -1mV (Figure 2) 1 ms T_ Settling Time tTS Measured between T_ input selection and AOUT settling to +1mV accuracy, CLOAD = 100pF, SC2 = 1 5 F s T_ Turn-On Delay Time tTD 0.2 F s VP Settling Time tVPS Measured between VP/12 (MAX14920), VP/16 (MAX14921) input selection and AOUT, settling to 2.5%, CLOAD = 100pF, SC3 = 1 25 60 F s Self-Calibration Time 8 ms THERMAL DETECTION Thermal Shutdown +140 °C Thermal-Shutdown Hysteresis 15 °C SPI TIMINGS (Figure 3) SDI to SCLK Setup tDS 50 ns SDI to SCLK Hold tDH 12 ns SCLK to SDO Valid tDO 100 ns CS Fall to SDO Enable tDV 100 ns CS Rise to SDO Disable tTR 80 ns CS Pulse Width tCSW 50 ns CS Fall to SCLK Rise Setup tCSS 100 ns CS Rise to SCLK Rise Hold tCSH 0 ns SCLK High Pulse Width tCH 65 ns SCLK Low Pulse Width tCL 65 ns SCLK Period tCP 208 ns |
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