5

Maxim Integrated

MAX14920/MAX14921

High-Accuracy 12-/16-Cell Measurement AFEs

DC ELECTRICAL CHARACTERISTICS (continued)

Note 3: Where n = 1–12 (MAX14920) and n = 1–16 (MAX14921).

fier errors and parasitic capacitance charge injection error. Since parasitic capacitance error is PCB dependent, output

error is guaranteed by design for a sampling capacitor of 1FF and parasitic capacitance less than 2.5pF on CTn (see the

Measurement Accuracy section for a detailed explanation).

Note 5: Buffer amplifier self-calibrates its offset at power-up and every time it is requested. Due to possible thermal drift after

power-up phase, it is suggested to run self-calibration on a regular basis to get best performance

(see the Buffer Amplifier Offset Calibration section for a detailed explanation).

Note 6: Amplifier error is the sum of all errors including amplifier offset and gain error.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Level-Shifting Delay Time

Delay from SMPLB set to 1 or SAMPL

falling edge to shifting of all cell voltages

to ground and available for reading

25

50

F

s

AOUT Voltage-Droop Time

Droop to -1mV (Figure 2)

1

ms

T_ Settling Time

Measured between T_ input selection

and AOUT settling to +1mV accuracy,

5

F

s

T_ Turn-On Delay Time

0.2

F

s

AOUT, settling to 2.5%,

25

60

F

s

Self-Calibration Time

8

ms

THERMAL DETECTION

Thermal Shutdown

+140

°C

Thermal-Shutdown Hysteresis

15

°C

SPI TIMINGS (Figure 3)

SDI to SCLK Setup

50

ns

SDI to SCLK Hold

12

ns

SCLK to SDO Valid

100

ns

CS Fall to SDO Enable

100

ns

CS Rise to SDO Disable

80

ns

CS Pulse Width

50

ns

CS Fall to SCLK Rise Setup

100

ns

CS Rise to SCLK Rise Hold

0

ns

SCLK High Pulse Width

65

ns

SCLK Low Pulse Width

65

ns

SCLK Period

208

ns