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DP83640TVV Datasheet(PDF) 49 Page - Texas Instruments |
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DP83640TVV Datasheet(HTML) 49 Page - Texas Instruments |
49 / 136 page DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 5.10.2.1 Link Quality Monitor Control and Status Control of the Link Quality Monitor is done through the Link Quality Monitor Register (LQMR), address 1Dh and the Link Quality Data Register (LQDR), address 1Bh of the Link Diagnostics Registers - Page 2. The LQMR register includes a global enable to enable the Link Quality Monitor function. In addition, it provides warning status from both high and low thresholds for each of the monitored parameters except SNR Variance.. The LQMR2 register provides warning status for the high threshold of SNR Variance (upper 16 bits); there is no low threshold. Note that individual low or high parameter threshold comparisons can be disabled by setting to the minimum or maximum values. To allow the Link Quality Monitor to interrupt the system, the Interrupt must be enabled through the interrupt control registers, MICR (11h) and MISR (12h). The Link Quality Monitor may also be used to automatically reset the DSP and restart adaption. Separate enable bits in LQMR and LQMR2 allow for automatic reset based on each of the parameter values. If enabled, a violation of one of the thresholds will result in a restart of the DSP adaption. In addition if the PCSR:SD_OPTION register bit is set to 0, the violation will also result in a drop in Link Status. 5.10.2.2 Checking Current Parameter Values Prior to setting Threshold values, it is recommended that software check current adapted values. The thresholds may then be set relative to the adapted values. The current adapted values can be read using the LQDR register by setting the SAMPLE_PARAM bit [13] of LQDR, address (1Eh). For example, to read the DBLW current value: 1. Write 2400h to LQDR (1Eh) to set the SAMPLE_PARAM bit and set the LQ_PARAM_SEL[2:0] to 010. 2. Read LQDR (1Eh). Current DBLW value is returned in the low 8 bits. 5.10.2.3 Threshold Control The LQDR (1Eh) register also provides a method of programming high and low thresholds for each of the five parameters that can be monitored. The register implements an indirect read/write mechanism. Writes are accomplished by writing data, address, and a write strobe to the register. Reads are accomplished by writing the address to the register, and reading back the value of the selected threshold. Setting thresholds to the maximum or minimum values will disable the threshold comparison since values have to exceed the threshold to generate a warning condition. Warnings are not generated if the parameter is equal to the threshold. By default, all thresholds are disabled by setting to the minimum or maximum values. The Table 5-4 shows the five parameters and range of values: Table 5-4. Link Quality Monitor Parameter Ranges Parameter Minimum Value Maximum Value Min (2-s comp) Max (2-s comp) DEQ_C1 -128 +127 0x80 0x7F DAGC 0 +255 0x00 0xFF DBLW -128 +127 0x80 0x7F Frequency Offset -128 +127 0x80 0x7F Frequency Control -128 +127 0x80 0x7F SNR Variance 0 +2304 0x0000 0x900 Note that values are signed 2-s complement values except for DAGC and Variance which are always positive. The maximum SNR Variance is calculated by assuming the worst-case squared error (144) is accumulated every 8 ns for 8*220 ns (roughly 8 ms or exactly 1,048,576 clock cycles). For example, to set the DBLW Low threshold to -38: 1. Write 14DAh to LQDR to set the Write_LQ_Thr bit, select the DBLW Low Threshold, and write data of -38 (0xDA). Copyright © 2007–2013, Texas Instruments Incorporated Configuration 49 Submit Documentation Feedback Product Folder Links: DP83640 |
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