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DP83640TVV Datasheet(PDF) 25 Page - Texas Instruments |
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DP83640TVV Datasheet(HTML) 25 Page - Texas Instruments |
25 / 136 page 10% 90% +1 rise +1 fall -1 fall -1 rise 90% 10% T2.8.1 T2.8.1 T2.8.1 T2.8.1 PMD Output Pair T2.8.2 PMD Output Pair eye pattern T2.8.2 TX_CLK TX_EN TXD[3:0] PMD Output Pair IDLE DATA (J/K) T2.7.1 DP83640 www.ti.com SNOSAY8E – SEPTEMBER 2007 – REVISED APRIL 2013 4.11 AC Specifications — 100BASE-TX and 100BASE-FX MII Transmit Packet Deassertion Timing Parameter Description Notes Min Typ Max Units T2.7.1 TX_CLK to PMD Output Pair 100BASE-TX and 100BASE-FX modes 5 bits Deassertion(1) (1) Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the first bit of the "T" code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100Mb/ mode Figure 4-7. 100BASE-TX and 100BASE-FX MII Transmit Packet Deassertion Timing 4.12 AC Specifications — 100BASE-TX Transmit Timing (tR/F & Jitter) Parameter Description Notes Min Typ Max Units T2.8.1 100 Mb/s PMD Output Pair tR and tF (1) 3 4 5 ns 100 Mb/s tR and tF Mismatch (2) 500 ps T2.8.2 100 Mb/s PMD Output Pair Transmit Jitter 1.4 ns (1) Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude (2) Normal Mismatch is the difference between the maximum and minimum of all rise and fall times Figure 4-8. 100BASE-TX Transmit Timing (tR/F & Jitter) Copyright © 2007–2013, Texas Instruments Incorporated Electrical Specifications 25 Submit Documentation Feedback Product Folder Links: DP83640 |
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