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ADM1065ASUZ Datasheet(PDF) 17 Page - Analog Devices
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ADM1065ASUZ Datasheet(HTML) 17 Page - Analog Devices
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Rev. D | Page 17 of 28
Monitoring Fault Detector
The monitoring fault detector block is used to detect a failure
on an input. The logical function implementing this is a wide
OR gate that can detect when an input deviates from its expected
condition. The clearest demonstration of the use of this block
is in the PWRGD state, where the monitor block indicates that
a failure on one or more of the VP1, VP2, or VP3 inputs has
No programmable delay is available in this block because the
triggering of a fault condition is likely to be caused by a supply
falling out of tolerance. In this situation, the device needs to
react as quickly as possible. Some latency occurs when moving
out of this state, however, because it takes a finite amount of time
(~20 μs) for the state configuration to download from the
EEPROM into the SE. Figure 23 is a block diagram of the
monitoring fault detector.
LOGIC INPUT CHANGE
OR FAULT DETECTION
Figure 23. Monitoring Fault Detector Block Diagram
The timeout detector allows the user to trap a failure to ensure
proper progress through a power-up or power-down sequence.
In the sample application shown in Figure 22, the timeout next-
state transition is from the EN3V3 and EN2V5 states. For the
EN3V3 state, the signal 3V3ON is asserted on the PDO1 output
pin upon entry to this state to turn on a 3.3 V supply. This supply
rail is connected to the VP2 pin, and the sequence detector looks
for the VP2 pin to go above its undervoltage threshold, which is
set in the supply fault detector (SFD) attached to that pin.
The power-up sequence progresses when this change is detected.
If, however, the supply fails (perhaps due to a short circuit
overloading this supply), the timeout block traps the problem.
In this example, if the 3.3 V supply fails within 10 ms, the SE
moves to the DIS3V3 state and turns off this supply by bringing
PDO1 low. It also indicates that a fault has occurred by taking
PDO3 high. Timeout delays of 100 μs to 400 ms can be
FAULT AND STATUS REPORTING
The ADM1065 has a fault latch for recording faults. Two registers,
FSTAT1 and FSTAT2, are set aside for this purpose. A single bit
is assigned to each input of the device, and a fault on that input sets
the relevant bit. The contents of the fault register can be read
out over the SMBus to determine which input(s) faulted. The
fault register can be enabled or disabled in each state. To latch
data from one state, ensure that the fault latch is disabled in the
following state. This ensures that only real faults are captured and
not, for example, undervoltage conditions that may be present
during a power-up or power-down sequence.
The ADM1065 also has a number of status registers. These
include more detailed information, such as whether an under-
voltage or overvoltage fault is present on a particular input. The
status registers also include information on ADC limit faults. Note
that the data in the status registers is not latched in any way and,
therefore, is subject to change at any time.
See the AN-698 Application Note at www.analog.com for full
details about the ADM1065 registers.
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