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SLDS145B Datasheet(PDF) 3 Page - Texas Instruments |
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SLDS145B Datasheet(HTML) 3 Page - Texas Instruments |
3 / 29 page TFP410 TI PanelBus™ DIGITAL TRANSMITTER SLDS145B − OCTOBER 2001 − REVISED MAY 2011 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram 12/24 Bit I/F Data Format Universal Input T.M.D.S. Transmitter Serializer Serializer Serializer Control I2C Slave I/F For DDC 1.8-V Regulators With Bypass Capacitors PLL TX2± TX1± TX0± TXC± TFADJ IDCK± DATA[23:0] DE VSYNC HSYNC EDGE/HTPLG MSEN PD ISEL/RST BSEL/SCL DSEL/SDA VREF Encoder Encoder Encoder CTL/A/DK[3:1] DKEN Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION Input DATA[23:12] 36−47 I The upper 12 bits of the 24-bit pixel bus In 24-bit, single-edge input mode (BSEL = high), this bus inputs the top half of the 24-bit pixel bus. In 12-bit, dual-edge input mode (BSEL = low), these bits are not used to input pixel data. In this mode, the state of DATA[23:16] is input to the I2C register CFG. This allows 8 bits of user configuration data to be read by the graphics controller through the I2C interface (see the I2C register descriptions section). Note: All unused data inputs should be tied to GND or VDD. DATA[11:0] 50−55, 58−63 I The lower 12 bits of the 24-bit pixel bus/12-bit pixel bus input In 24-bit, single-edge input mode (BSEL = high), this bus inputs the bottom half of the 24-bit pixel bus. In 12-bit, dual-edge input mode (BSEL = low), this bus inputs 1/2 a pixel (12 bits) at every latch edge (both rising and falling) of the clock. IDCK− IDCK+ 56 57 I Differential clock input. The TFP410 supports both single-ended and fully differential clock input modes. In the single-ended clock input mode, the IDCK+ input (pin 57) should be connected to the single-ended clock source and the IDCK− input (pin 56) should be tied to GND. In the differential clock input mode, the TFP410 uses the crossover point between the IDCK+ and IDCK− signals as the timing reference for latching incoming data DATA[23:0], DE, HSYNC, & VSYNC. The differential clock input mode is only available in the low signal swing mode. DE 2 I Data enable. As defined in DVI 1.0 specification, the DE signal allows the transmitter to encode pixel data or control data on any given input clock cycle. During active video (DE = high), the transmitter encodes pixel data, DATA[23:0]. During the blanking interval (DE = low), the transmitter encodes HSYNC, VSYNC and CTL[3:1]. HSYNC 4 I Horizontal sync input VSYNC 5 I Vertical sync input |
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