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CD4094BCN Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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CD4094BCN Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 7 page October 1987 Revised January 1999 © 1999 Fairchild Semiconductor Corporation DS005983.prf www.fairchildsemi.com CD4094BC 8-Bit Shift Register/Latch with 3-STATE Outputs General Description The CD4094BC consists of an 8-bit shift register and a 3- STATE 8-bit latch. Data is shifted serially through the shift register on the positive transition of the clock. The output of the last stage (QS) can be used to cascade several devices. Data on the QS output is transferred to a second output, Q ′ S, on the following negative clock edge. The output of each stage of the shift register feeds a latch, which latches data on the negative edge of the STROBE input. When STROBE is HIGH, data propagates through the latch to 3-STATE output gates. These gates are enabled when OUTPUT ENABLE is taken HIGH. Features s Wide supply voltage range: 3.0V to 18V s High noise immunity: 0.45 VDD (typ.) s Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS s 3-STATE outputs Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP and SOIC Top View Truth Table X = Don't Care = HIGH-to-LOW = LOW-to-HIGH Note 1: At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and QS. Order Number Package Number Package Description CD4094BCWM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide CD4094BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Clock Output Strobe Data Parallel Outputs Serial Outputs Enable Q1 QN QS (Note 1) Q ′Σ 0 X X Hi-Z Hi-Z Q7 No Change 0 X X Hi-Z Hi-Z No Change Q7 1 0 X No Change No Change Q7 No Change 11 0 0 QN−1 Q7 No Change 11 1 1 QN−1 Q7 No Change 1 1 1 No Change No Change No Change Q7 |
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