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MPC953 Datasheet(PDF) 3 Page - Motorola, Inc

Part No. MPC953
Description  LOW VOLTAGE PLL CLOCK DRIVER
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MPC953 Datasheet(HTML) 3 Page - Motorola, Inc

   
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MPC953
ECLinPS and ECLinPS Lite
DL140 — Rev 3
3
MOTOROLA
DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
VIH
Input HIGH Voltage LVCMOS Inputs
2.0
3.6
V
VIL
Input LOW Voltage LVCMOS Inputs
0.8
V
VPP
Peak–to–Peak Input Voltage PECL_CLK
300
1000
mV
VCMR
Common Mode Range
PECL_CLK
VCC–1.5
VCC–0.6
mV
Note 1.
VOH
Output HIGH Voltage
2.4
V
IOH = –40mA, Note 2.
VOL
Output LOW Voltage
0.5
V
IOL = 40mA, Note 2.
IIN
Input Current
±120
µA
CIN
Input Capacitance
4
pF
Cpd
Power Dissipation Capacitance
25
pF
Per Output
ICC
Maximum Quiescent Supply Current
75
mA
All VCC Pins
ICCPLL
Maximum PLL Supply Current
15
20
mA
VCCA Pin Only
1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within
the VCMR range and the input swing lies within the VPP specification.
2. The MPC953 outputs can drive series or parallel terminated 50
Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications
Info section).
PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C)
Symbol
Characteristic
Min
Max
Unit
Condition
fref
Reference Input Frequency
Note 3.
Note 3.
MHz
frefDC
Reference Input Duty Cycle
25
75
%
3. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.
AC CHARACTERISTICS (TA = 0°C to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
tr, tf
Output Rise/Fall Time
0.10
1.0
ns
0.8 to 2.0V
tpw
Output Duty Cycle
45
50
55
%
tsk(O)
Output–to–Output Skews (Relative to QFB)
±75
ps
fVCO
PLL VCO Lock Range
200
350
MHz
fmax
Maximum Output Frequency
50
87.5
MHz
VCO_SEL = ‘0’
tpd(lock)
Input to Ext_FB Delay (with PLL Locked)
X–100
X
(Note 4.)
X+100
ps
fref = 75MHz
tpd(bypass)
Input to Q Delay (with PLL Bypassed)
5
10
ns
tPLZ,HZ
Output Disable Time
7
ns
tPZL
Output Enable Time
6
ns
tjitter
Cycle–to–Cycle Jitter (Peak–to–Peak)
100
ps
tlock
Maximum PLL Lock Time
10
ms
4. X will be targeted for 0ns, but may vary from target by
±150ps based on characterization of silicon.


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