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MPC952 Datasheet(PDF) 1 Page - Motorola, Inc

Part No. MPC952
Description  LOW VOLTAGE PLL CLOCK DRIVER
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MPC952 Datasheet(HTML) 1 Page - Motorola, Inc

   
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1
REV 3
© Motorola, Inc. 1998
2/98
Low Voltage PLL Clock Driver
The MPC952 is a 3.3V compatible, PLL based clock driver device
targeted for high performance clock tree applications. The device
features a fully integrated PLL with no external components required.
With output frequencies of up to 180MHz and eleven low skew outputs
the MPC952 is well suited for high performance designs. The device
employs a fully differential PLL design to optimize jitter and noise
rejection performance. Jitter is an increasingly important parameter as
more microprocessors and ASiC’s are employing on chip PLL clock
distribution.
Fully Integrated PLL
Output Frequency up to 180MHz
High Impedance Disabled Outputs
Compatible with PowerPC™, Intel and High Performance RISC
Microprocessors
Output Frequency Configurable
TQFP Packaging
±100ps Cycle–to–Cycle Jitter
The MPC952 features three banks of individually configurable outputs.
The banks contain 5 outputs, 4 outputs and 2 outputs. The internal divide
circuitry allows for output frequency ratios of 1:1, 2:1, 3:1 and 3:2:1. The
output frequency relationship is controlled by the fsel frequency control
pins. The fsel pins as well as the other inputs are LVCMOS/LVTTL
compatible inputs.
The MPC952 uses external feedback to the PLL. This features allows
for the use of the device as a “zero delay” buffer. Any of the eleven
outputs can be used as the feedback to the PLL. The VCO_Sel pin allows for the choice of two VCO ranges to optimize PLL
stability and jitter performance. The MR/OE pin allows the user to force the outputs into high impedance for board level test.
For system debug the PLL of the MPC952 can be bypassed. When forced to a logic HIGH, the PLLEN input will route the
signal on the RefClk input around the PLL directly to the internal dividers. Because the signal is routed through the dividers, it
may take several transitions of the RefClk to affect a transition on the outputs. This features allows a designer to single step the
design for debug purposes.
The outputs of the MPC952 are LVCMOS outputs. The outputs are optimally designed to drive terminated transmission lines.
For applications using series terminated transmission lines each MPC952 output can drive two lines. This capability provides an
effective fanout of 22, more than enough clocks for most clock tree designs. For more information on driving transmission lines
consult the applications section of this data sheet.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
MPC952
LOW VOLTAGE
PLL CLOCK DRIVER
FA SUFFIX
TQFP PACKAGE
CASE 873A-02


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