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SAB82525N Datasheet(PDF) 74 Page - Siemens Semiconductor Group |
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SAB82525N Datasheet(HTML) 74 Page - Siemens Semiconductor Group |
74 / 126 page ![]() Semiconductor Group 74 SAB 82525 SAB 82526 SAF 82525 SAF 82526 The activities during frame transmission (supposed two frames, 18 bytes and 52 bytes) is shown in figure 35. Figure 35 Continuous Frames Transmission Sequence Example Serial Interface HSCX CPU Interface ITD00249 18 WR XTF Bytes 18 . . . XME . . . 32 Bytes WR XTF WR Bytes 20 . . . XTF XPR XTF + XME XPR ITF Bytes 32 Frame 1 Bytes Frame 2 Bytes 20 ITF XPR XPR DMA Mode Prior to the data transmission, the length of the next frame to be transmitted must be programmed via the Transmit Byte Count Registers (XBCH, XBCL). The resulting byte count equals the programmed value plus one byte, i.e. since 12 bits are provided via XBCH, XBCL (XBC11. . .XBC0) a frame length of 1 up to 4096 bytes (4 Kbytes) can be selected. After this, data transmission can be initiated by command (XTF or XIF). The HSCX will then autonomously request the correct amount of write bus cycles by activating the DRQT line. Depending on the programmed frame length, block data transfers of n × 32-bytes + remainder (n = 0, 1,…128) are requested everytime a 32-byte FIFO half (transmit pool) is empty and accessible to the DMA controller. |
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