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74VHCT574AN Datasheet(PDF) 4 Page - Fairchild Semiconductor |
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74VHCT574AN Datasheet(HTML) 4 Page - Fairchild Semiconductor |
4 / 8 page www.fairchildsemi.com 4 Noise Characteristics Note 7: Parameter guaranteed by design. AC Electrical Characteristics Note 8: Parameter guaranteed by design. tOSLH |tPLH max tPLH min|; tOSHL |tPHL max tPHL min| Note 9: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) CPD * VCC * fIN ICC/8 (per F/F). The total CPD when n pcs. of the Octal D Flip-Flop operates can be calculated by the equation: CPD (total) 20 12n. AC Operating Requirements Symbol Parameter VCC (V) TA 25qC Units Conditions Typ Limits VOLP Quiet Output Maximum Dynamic VOL 5.0 1.2 1.6 V CL 50 pF (Note 7) VOLV Quiet Output Minimum Dynamic VOL 5.0 1.2 1.6 V CL 50 pF (Note 7) VIHD Minimum HIGH Level Dynamic Input Voltage 5.0 2.0 V CL 50 pF (Note 7) VILD Maximum LOW Level Dynamic Input Voltage 5.0 0.8 V CL 50 pF (Note 7) Symbol Parameter VCC TA 25qCTA 40qC to 85qC Units Conditions (V) Min Typ Max Min Max tPLH Propagation Delay 5.0 r 0.5 4.1 9.4 1.0 10.5 ns CL 15 pF tPHL Time 5.6 10.4 1.0 11.5 CL 50 pF tPZL 3-STATE Output 5.0 r 0.5 6.5 10.2 1.0 11.5 ns RL 1 k: CL 15 pF tPZH Enable Time 7.3 11.2 1.0 12.5 CL 50 pF tPLZ 3-STATE Output 5.0 r 0.5 7.0 11.2 1.0 12.0 ns RL 1 k: CL 50 pF tPHZ Disable Time tOSLH Output to 5.0 r 0.5 1.0 1.0 ns (Note 8) tOSHL Output Skew fMAX Maximum Clock 5.0 r 0.5 90 140 80 MHz CL 15 pF Frequency 85 130 75 CL 50 pF CIN Input 4 10 10 pF VCC Open Capacitance COUT Output 9 pF VCC 5.0V Capacitance CPD Power Dissipation 25 pF (Note 9) Capacitance Symbol Parameter VCC (V) TA 25qC TA 40qC to 85qC Units Min Typ Max Min Max tW(H) Minimum Pulse Width (CP) 5.0 r 0.5 6.5 8.5 ns tW(L) tS Minimum Set-Up Time 5.0 r 0.5 2.5 2.5 ns tH Minimum Hold Time 5.0 r 0.5 2.5 2.5 |
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