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ACE25C200 Datasheet(PDF) 9 Page - ACE Technology Co., LTD.

Part # ACE25C200
Description  2MB Serial Flash Memory
Download  32 Pages
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Manufacturer  ACE [ACE Technology Co., LTD.]
Direct Link  http://www.ace-ele.com
Logo ACE - ACE Technology Co., LTD.

ACE25C200 Datasheet(HTML) 9 Page - ACE Technology Co., LTD.

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ACE25C200
2MB Serial Flash Memory
VER 1.2
9
Status Register Protect bit / Lock_bit (SRP/LB)
The Status Register Protect (SRP) bit is operated in conjunction with the Write Protect (WP#) signal.
The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put
in the Hardware Protected mode (when the Status Register Protect (SRP) bit is set to 1, and Write
Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status Register (SRP, BP2,
BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer
accepted for execution.
In OTP mode, this bit is served as Lock_bit (LB), user can read/program/erase security sector as
normal sector while LB value is equal 0, after LB is programmed with 1 by WRSR command, the
security sector is protected from program and erase operation. The LB can only be programmed once.
Note: In OTP mode, the WRSR command will ignore any input data and program LB to 1, user must clear the protect bits
before enter OTP mode and program the OTP code, then execute WRSR command to lock the security sector before
leaving OTP mode.
Status Register Memory Protection
Status Register Content
Memory Content
BP2 bit
BP1 bit
BP0 bit
Protect Areas
Address
Density
Portion
0
0
0
None
None
None
None
0
0
1
Reserved State, not allowed
0
1
0
0
1
1
1
0
0
Sector 0~47
000000h~02FFFFh
192KB
Lower 48/64
1
0
1
Sector 0~31
000000h~01FFFFh
128KB
Lower 32/64
1
1
0
All
000000h~02FFFFh
256KB
All
1
1
1
All
000000h~03FFFFh
256KB
All
Instructions
The Standard/Dual SPI instruction set of the ACE25C200 consists of 17 basic instructions that are
fully controlled through the SPI bus (see Table 4~Table 5 Instruction Set). Instructions are initiated
with the falling edge of Chip Select (CS#). The first byte of data clocked into the DI input provides the
instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit
(MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes,
data byte
s, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed
with the rising edge of edge CS#. Clock relative timing diagrams for each instruction are included in
Figure 5 through Figure 27. All read instructions can be complet ed after any clocked bit. However, all
instructions that Write, Program or Erase must complete on a byte boundary (CS# driven high after a
full 8-bits have been clocked) otherwise the instruction will be ignored. This feature further protects
the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or
when the Status Register is being written, all instructions except for Read Status Register will be
ignored until the program or erase cycle has completed.


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