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2

Logic Symbol

IEEE/IEC

Connection Diagram

Pin Descriptions

Truth Table

Note 2: This configuration is nonstable; that is, it will not persist when pre-

set and clear inputs return to their inactive (HIGH) state.

Pin Names

Description

Data Inputs

Clock Pulse Inputs

Direct Clear Inputs

Direct Preset Inputs

Output

Inputs

Outputs

Function

CLR

PR

DCK

Q

Q

L

H

X

X

L

H

Clear

HL

X

X

H

L

Preset

L

L

X

X

H (Note 2) H (Note 2)

HH

L



LH

HH

H



HL

HH

X



No Change