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MCIMX6D4AVT08AC Datasheet(PDF) 86 Page - Freescale Semiconductor, Inc |
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MCIMX6D4AVT08AC Datasheet(HTML) 86 Page - Freescale Semiconductor, Inc |
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86 / 166 page  i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2 86 Freescale Semiconductor Electrical Characteristics 1 ENET_COL has the same timing in 10-Mbit 7-wire interface mode. 4.11.5.1.4 MII Serial Management Channel Timing (ENET_MDIO and ENET_MDC) The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3 MII specification. However the ENET can function correctly with a maximum MDC frequency of 15 MHz. Figure 51 shows MII asynchronous input timings. Table 61 describes the timing parameters (M10–M15) shown in the figure. Figure 51. MII Serial Management Channel Timing Diagram Table 60. MII Asynchronous Inputs Signal Timing ID Characteristic Min Max Unit M91 ENET_CRS to ENET_COL minimum pulse width 1.5 — ENET_TX_CLK period Table 61. MII Serial Management Channel Timing ID Characteristic Min Max Unit M10 ENET_MDC falling edge to ENET_MDIO output invalid (minimum propagation delay) 0— ns M11 ENET_MDC falling edge to ENET_MDIO output valid (maximum propagation delay) —5 ns M12 ENET_MDIO (input) to ENET_MDC rising edge setup 18 — ns M13 ENET_MDIO (input) to ENET_MDC rising edge hold 0 — ns M14 ENET_MDC pulse width high 40% 60% ENET_MDC period M15 ENET_MDC pulse width low 40% 60% ENET_MDC period ENET_MDC (output) ENET_MDIO (output) M14 M15 M10 M11 M12 M13 ENET_MDIO (input) |
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