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MCIMX6D4AVT08AC Datasheet(PDF) 42 Page - Freescale Semiconductor, Inc

Part # MCIMX6D4AVT08AC
Description  i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MCIMX6D4AVT08AC Datasheet(HTML) 42 Page - Freescale Semiconductor, Inc

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i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
42
Freescale Semiconductor
Electrical Characteristics
4.7.2
DDR I/O AC Parameters
The LPDDR2 interface mode fully complies with JESD209-2B LPDDR2 JEDEC standard release June,
2009. The DDR3/DDR3L interface mode fully complies with JESD79-3D DDR3 JEDEC standard release
April, 2008.
Table 30 shows the AC parameters for DDR I/O operating in LPDDR2 mode.
Table 31 shows the AC parameters for DDR I/O operating in DDR3/DDR3L mode.
Table 30. DDR I/O LPDDR2 Mode AC Parameters1
1 Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
AC input logic high
Vih(ac)
Vref + 0.22
OVDD
V
AC input logic low
Vil(ac)
0
Vref – 0.22
V
AC differential input high voltage2
2 Vid(ac) specifies the input differential voltage |Vtr – Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac).
Vidh(ac)
0.44
V
AC differential input low voltage
Vidl(ac)
0.44
V
Input AC differential cross point voltage3
3 The typical value of Vix(ac) is expected to be about 0.5
 OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
Vix(ac)
Relative to Vref
-0.12
0.12
V
Over/undershoot peak
Vpeak
0.35
V
Over/undershoot area (above OVDD
or below OVSS)
Varea
533 MHz
0.3
V-ns
Single output slew rate, measured
between Vol(ac) and Voh(ac)
tsr
50
to Vref.
5 pF load.
Drive impedance = 4 0
30%
1.5
3.5
V/ns
50
to Vref.
5pF load.
Drive impedance = 60
30%
1—
2.5
Skew between pad rise/fall asymmetry +
skew caused by SSN
tSKD
clk = 533 MHz
——
0.1
ns
Table 31. DDR I/O DDR3/DDR3L Mode AC Parameters1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
AC input logic high
Vih(ac)
Vref + 0.175
OVDD
V
AC input logic low
Vil(ac)
0
Vref – 0.175
V
AC differential input voltage2
Vid(ac)
0.35
V
Input AC differential cross point voltage3
Vix(ac)
Relative to Vref
Vref – 0.15
Vref + 0.15
V
Over/undershoot peak
Vpeak
0.4
V
Over/undershoot area (above OVDD
or below OVSS)
Varea
533 MHz
0.5
V-ns


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