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74VHC595 Datasheet(PDF) 5 Page - Fairchild Semiconductor

Part No. 74VHC595
Description  8-Bit Shift Register with Output Latches
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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74VHC595 Datasheet(HTML) 5 Page - Fairchild Semiconductor

   
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AC Electrical Characteristics
Note 4: Parameter guaranteed by design. tOSLH = | tPLH max − tPLH min|; tOSHL = | tPHL max − tPHL min|.
Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: ICC (opr.) = CPD * VCC * fIN + ICC.
Symbol
Parameter
VCC
(V)
TA = +25°CTA = −40°C to +85°C
Units
Conditions
Min
Typ
Max
Min
Max
tPLH
Propagation Delay Time
3.3
± 0.3
7.7
11.9
1.0
13.5
ns
CL = 15 pF
tPHL
RCK to QA–QH
10.2
15.4
1.0
17.0
CL = 50 pF
5.0
± 0.5
5.4
7.4
1.0
8.5
ns
CL = 15 pF
6.9
9.4
1.0
10.5
CL = 50 pF
tPLH
Propagation Delay Time
3.3
± 0.3
8.8
13.0
1.0
15.0
ns
CL = 15 pF
tPHL
SCK–Q'H
11.3
16.5
1.0
18.5
CL = 50 pF
5.0
± 0.5
6.2
8.2
1.0
9.4
ns
CL = 15 pF
7.7
10.2
1.0
11.4
CL = 50 pF
tPHL
Propagation Delay Time
3.3
± 0.3
8.4
12.8
1.0
13.7
ns
CL = 15 pF
SCLR –Q'H
10.9
16.3
1.0
17.2
CL = 50 pF
5.0
± 0.5
5.9
8.0
1.0
9.1
ns
CL = 15 pF
7.4
10.0
1.0
11.1
CL = 50 pF
tPZL
Output Enable Time
3.3
± 0.3
7.5
11.5
1.0
13.5
ns
RL = 1 kΩ
CL = 15 pF
tPZH
G to QA–QH
9.0
15.0
1.0
17.0
CL = 50 pF
5.0
± 0.5
4.8
8.6
1.0
10.0
ns
CL = 15 pF
8.3
10.6
1.0
12.0
CL = 50 pF
tPLZ
Output Disable Time
3.3
± 0.3
12.1
15.7
1.0
16.2
ns
RL = 1 kΩ
CL = 50 pF
tPHZ
G to QA–QH
5.0
± 0.5
7.6
10.3
1.0
11.0
CL = 50 pF
fMAX
Maximum Clock
3.3
± 0.3
80
150
70
MHz
CL = 15 pF
Frequency
55
130
50
CL = 50 pF
5.0
± 0.5
135
185
115
MHz
CL = 15 pF
95
155
85
CL = 50 pF
tOSLH
Output to Output
3.3
± 0.3
1.5
1.5
ns
(Note 4)
CL = 50 pF
tOSHL
Skew
5.0
± 0.5
1.0
1.0
CL = 50 pF
CIN
Input Capacitance
5.0
10
10
pF
VCC = Open
COUT
Output Capacitance
6.0
pF
VCC = 5.0V
CPD
Power Dissipation
87
pF
(Note 5)
Capacitance


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