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MPC2605ZP66 Datasheet(PDF) 11 Page - Motorola, Inc |
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MPC2605ZP66 Datasheet(HTML) 11 Page - Motorola, Inc |
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11 / 30 page  MPC2605 11 MOTOROLA that the processor’s bus grant is negated once there are two outstanding data transactions. It is expected that most sys- tems will tie CFG4 high. RESET/INITIALIZATION To ensure proper initialization and system functionality, the HRESET pin of the MPC2605 should be connected to the same signal that is used to reset the processor. The TRST signal must be negated before HRESET is negated. When HRESET is negated, the MPC2605 commences an internal initialization sequence to clear all of the valid bits in the cache. The sequence takes approximately 4000 clock cycles. During this time the MPC2605 will not participate in any bus transaction that occurs. All transactions are, howev- er, monitored so that, regardless of when the initialization se- quence completes, the MPC2605 is prepared to take action on the next transaction initiated by the processor. At some point after this 4000 cycle sequence, the MPC2605 will detect its first cache hit. At this time the system will experience its first assertion of L2 CLAIM. If the memory controller must be configured via software to comprehend assertions of L2 CLAIM, this configuration operation must have completed by this time. For systems that cannot guar- antee that this requirement is met, it is necessary to disable the MPC2605 until such time as this configuration can be guaranteed. Disabling the MPC2605 can be accomplished by asserting L2 UPDATE INH sometime during reset and ne- gating it when it is deemed safe for caching to commence. 60X BUS OPERATION All transactions have what is called an address tenure. An address tenure is a set number of bus cycles during which the address bus and its associated control signals are being used for the transaction at hand. In general, there are two types of transactions. Those that only have address tenures, called address–only transactions. And those that require the use of the data bus and therefore will have a data tenure. These transactions are called data transactions. This section describes how address and data tenures are defined as viewed by the MPC2605. Address Tenures Address tenures on the 60X bus are fairly well defined. They start with an assertion of TS by a device that has been granted the bus by the system arbiter. This device is called the bus master for this transaction. At the same time that TS is asserted, the bus master also drives the address and all other relevant control signals that define the transaction. TS is only asserted for one cycle but all other signals are held valid by the bus master until some other device asserts AACK. The device that asserts AACK becomes the slave to this transaction. Typically, the slave is the memory controller, although for transactions that are cache hits the MPC2605 becomes the slave by driving L2 CLAIM. Transactions can be aborted by any device on the bus by asserting ARTRY. ARTRY may be asserted at any time after TS is asserted, but must be held through the cycle after AACK is asserted. This cycle is referred to as the ARTRY window, since it is the cycle in which all devices sample ARTRY to determine if the address tenure has completed successfully. If an address tenure is not aborted by an assertion of ARTRY, then the next bus master is free to assert TS, the cycle after the ARTRY window to start a new address tenure. If ARTRY is asserted in the ARTRY window, all devices that are not asserting ARTRY must negate their bus request in the following cycle. This next cycle is called the BR window. The purpose of this protocol is to give immediate bus master- ship to the device that asserted ARTRY with the expectation that that device will take this opportunity to clean up what- ever circumstances caused it to assert ARTRY. Typically, this involves writing data back to memory to maintain coherence in the system. Data Tenures Data tenures are more complicated to define than address tenures. They require two conditions to start: an assertion of TS that initiates a data transaction and a qualified assertion of the bus master’s data bus grant. For a data bus grant to be considered qualified, no device on the bus may be asserting DBB in the cycle that the data bus grant is asserted. Data transactions come in two types: single–beat transac- tions and burst transactions. The type is determined by the state of TBST during the address tenure of the transaction. If the bus master asserts TBST, the transaction is a burst trans- action and will require four assertions of TA in order to com- plete normally. If TBST is negated during the address tenure, the transaction only requires one assertion of TA, thus the name single–beat. Which device drives the data bus during a data transaction depends upon whether the transaction is a read or a write. For a read transaction, the slave device drives the data bus. For a write transaction, the master drives the data bus. In all data transactions, the slave device asserts TA to indicate that either valid data is present on the bus, in the case of a read; or that it is reading data off the data bus, in the case of a write. The master device asserts DBB the cycle after it has been granted the data bus and keeps it asserted until the data tenure has completed. A data tenure can be aborted in two different ways. The address tenure for the transaction can be aborted by an assertion of ARTRY. Or, the slave device may assert TEA to indicate that some error condition has been detected. Either event will prematurely terminate the data tenure. Data Streaming For the majority of data transactions there must be a wait state between the completion of one data tenure and the start of the next. This turnaround cycle avoids the contention on the data bus that would occur if one device starts driving data before another device has had a chance to turn off its data bus drivers. When a cache read hit is pipelined on top of another cache read hit, there is no need for this turnaround cycle since the same device will be driving the data bus for both data tenures. The 60X bus has the ability to remove this unnecessary wait state and allow back–to–back cache read hits to stream together. This ability is only enabled if the sys- tem is put into Fast L2 mode. Note that not all PowerPC pro- cessors support Fast L2 mode. One of the requirements for taking advantage of this data streaming capability is that the system arbiter must be sophisticated enough to identify situations in which stream- ing may occur. Upon recognizing these situations, it must as- sert the processor’s data bus grant in the cycle coincident |
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