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MPC2107SG15 Datasheet(PDF) 9 Page - Motorola, Inc |
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MPC2107SG15 Datasheet(HTML) 9 Page - Motorola, Inc |
9 / 24 page MPC2104 •MPC2105•MPC2106•MPC2107 9 MOTOROLA FAST SRAM DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 5% TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level 1.5 V . . . . . . . . . . . . . . . Input Pulse Levels 0 to 3.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Rise/Fall Time 3 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Timing Reference Level 1.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . Output Load See Figure 1A Unless Otherwise Noted . . . . . . . . . . . . SYNCHRONOUS DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 7) MPC2104 MPC2105 MPC2106 Parameter Symbol Min Max Unit Notes Cycle Time tKHKH 15 — ns Clock Access Time tKHQV — 9 ns 4 Output Enable to Output Valid tGLQV — 5 ns Clock High to Output Active tKHQX1 6 — ns Clock High to Output Change tKHQX2 3 — ns Output Enable to Output Active tGLQX 0 — ns Output Disable to Q High–Z tGHQZ 2 6 ns Clock High to Q High–Z tKHQZ — 6 ns Clock High Pulse Width tKHKL 5 — ns Clock Low Pulse Width tKLKH 5 — ns Setup Time Address tAVKH 7.5 — ns 5, 6 Setup Times: Address Status Data In Write Address Advance Chip Enable tSVKH tDVKH tWVKH tBAVVKH tEVKH 2.5 — ns 5 Hold Times: Address Address Status Data In Write Address Advance Chip Enable tKHAX tKHTSX tKHDX tKHWX tKHBAX tKHEX 0.5 — ns 5 NOTES: 1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW. 2. All read and write cycle timings are referenced from CLK or COE. 3. COE is a don’t care when UW or LW is sampled low. 4. Maximum access times are guaranteed for all possible PowerPC external bus cycles. 5. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of CLK whenever TSP or TSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of CLK when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when TSP or TSC is low) to remain enabled. 6. 5 ns of set–up delay is incurred in address buffers. 7. Applies to MPC2104, MPC2105, and MPC2106. |
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