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74VHC161284MEAX Datasheet(PDF) 5 Page - Fairchild Semiconductor |
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74VHC161284MEAX Datasheet(HTML) 5 Page - Fairchild Semiconductor |
5 / 11 page 5 www.fairchildsemi.com AC Electrical Characteristics Note 8: Open Drain Note 9: tSKEW is measured for common edge output transitions and compares the measured propagation delay for a given path type. (i) A1–A8 to B1–B8, A9–Y13 to Y9–Y13 (ii) B1–B8 to A1–A8 (iii) C14–C17 to A14–A17 Note 10: This parameter is guaranteed but not tested, characterized only. Capacitance (Note 11) Note 11: Capacitance is measured at frequency 1 MHz. Symbol Parameter TA 40qC to 85qC Units Figure Number VCC 4.5V 5.5V Min Max tPHL A1–A8 to B1–B8 2.0 30.0 ns Figure 1 tPLH A1–A8 to B1–B8 2.0 30.0 ns Figure 2 tPHL B1–B8 to A1–A8 2.0 30.0 ns Figure 3 tPLH B1–B8 to A1–A8 2.0 30.0 ns Figure 3 tPHL A9–A13 to Y9–Y13 2.0 30.0 ns Figure 1 tPLH A9–A13 to Y9–Y13 2.0 30.0 ns Figure 2 tPHL C14–C17 to A14–A17 2.0 30.0 ns Figure 3 tPLH C14–C17 to A14–A17 2.0 30.0 ns Figure 3 tSKEW LH-LH or HL-HL 6.0 ns (Note 9) tPHL PLHIN to PLH 2.0 30.0 ns Figure 1 tPLH PLHIN to PLH 2.0 30.0 ns Figure 2 tPHL HLHIN to HLH 2.0 30.0 ns Figure 3 tPLH HLHIN to HLH 2.0 30.0 ns Figure 3 tPHZ Output Disable Time 2.0 18.0 ns Figure 7 tPLZ DIR to A1–A8 2.0 18.0 tPZH Output Enable Time 2.0 25.0 ns Figure 8 tPZL DIR to A1–A8 2.0 25.0 tPHZ Output Disable Time 2.0 25.0 ns Figure 9 tPLZ DIR to B1–B8 2.0 25.0 tpEN Output Enable Time 2.0 28.0 ns Figure 2 HD to B1–B8, Y9–Y13 tpDis Output Disable Time 2.0 28.0 ns Figure 2 HD to B1–B8, Y9–Y13 tpEn–tpDis Output Enable-Output Disable 20.0 ns tSLEW Output Slew Rate tPLH B1–B8, Y9–Y13 0.05 0.40 V/ns Figure 5 tPHL 0.05 0.40 Figure 4 tr, tf tRISE and tFALL 120 ns Figure 6 B1–B8, Y9–Y13 (Note 8) 120 (Note 10) Symbol Parameter Typ Units Conditions CIN Input Capacitance 5 pF VCC 0.0V (HD, DIR, A9—A13, C14—C17, PLHIN and HLHIN) CI/O I/O Pin Capacitance 12 pF VCC 3.3V |
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