Electronic Components Datasheet Search
  English  ▼

Delete All


Preview PDF Download HTML

74VHC163 Datasheet(PDF) 2 Page - Fairchild Semiconductor

Part No. 74VHC163
Description  4-Bit Binary Counter with Synchronous Clear
Download  10 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74VHC163 Datasheet(HTML) 2 Page - Fairchild Semiconductor

  74VHC163 Datasheet HTML 1Page - Fairchild Semiconductor 74VHC163 Datasheet HTML 2Page - Fairchild Semiconductor 74VHC163 Datasheet HTML 3Page - Fairchild Semiconductor 74VHC163 Datasheet HTML 4Page - Fairchild Semiconductor 74VHC163 Datasheet HTML 5Page - Fairchild Semiconductor 74VHC163 Datasheet HTML 6Page - Fairchild Semiconductor 74VHC163 Datasheet HTML 7Page - Fairchild Semiconductor 74VHC163 Datasheet HTML 8Page - Fairchild Semiconductor 74VHC163 Datasheet HTML 9Page - Fairchild Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 2 / 10 page
background image
Connection Diagram
Pin Descriptions
Functional Description
The VHC163 counts in modulo-16 binary sequence. From
state 15 (HHHH) it increments to state 0 (LLLL). The clock
inputs of all flip-flops are driven in parallel through a clock
buffer. Thus all changes of the Q outputs occur as a result
of, and synchronous with, the LOW-to-HIGH transition of
the CP input signal. The circuits have four fundamental
modes of operation, in order of precedence: synchronous
reset, parallel load, count-up and hold. Four control
inputs—Synchronous Reset (MR), Parallel Enable (PE),
Count Enable Parallel (CEP) and Count Enable Trickle
(CET)—determine the mode of operation, as shown in the
Mode Select Table. A LOW signal on MR overrides count-
ing and parallel loading and allows all outputs to go LOW
on the next rising edge of CP. A LOW signal on PE over-
rides counting and allows information on the Parallel Data
(Pn) inputs to be loaded into the flip-flops on the next rising
edge of CP. With PE and MR HIGH, CEP and CET permit
counting when both are HIGH. Conversely, a LOW signal
on either CEP or CET inhibits counting.
The VHC163 uses D-type edge-triggered flip-flops and
changing the MR, PE, CEP and CET inputs when the CP is
in either state does not cause errors, provided that the rec-
ommended setup and hold times, with respect to the rising
edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 15. To implement synchro-
nous multistage counters, the TC outputs can be used with
the CEP and CET inputs in two different ways.
Figure 1 shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC
delay of the first stage, plus the cumulative CET to TC
delays of the intermediate stages, plus the CET to CP
setup time of the last stage. This total delay plus setup time
sets the upper limit on clock frequency. For faster clock
rates, the carry lookahead connections shown in Figure 2
are recommended. In this scheme the ripple delay through
the intermediate stages commences with the same clock
that causes the first stage to tick over from max to min to
start its final cycle. Since this final cycle takes 16 clocks to
complete, there is plenty of time for the ripple to progress
through the intermediate stages. The critical timing that lim-
its the clock period is the CP to TC delay of the first stage
plus the CEP to CP setup time of the last stage. The TC
output is subject to decoding spikes due to internal race
conditions and is therefore not recommended for use as a
clock or asynchronous reset for flip-flops, registers or
Logic Equations: Count Enable
= CEP • CET • PE
= Q
0 • Q1 • Q 2 • Q3 • CET
Pin Names
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
Synchronous Master Reset Input
Parallel Data Inputs
Parallel Enable Inputs
Flip-Flop Outputs
Terminal Count Output

Html Pages

1  2  3  4  5  6  7  8  9  10 

Datasheet Download

Go To PDF Page

Link URL

Privacy Policy
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com

Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn