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74VHC161 Datasheet(PDF) 2 Page - Fairchild Semiconductor

Part No. 74VHC161
Description  4-Bit Binary Counter with Asynchronous Clear
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74VHC161 Datasheet(HTML) 2 Page - Fairchild Semiconductor

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Connection Diagram
Pin Descriptions
Functional Description
The VHC161 counts in modulo-16 binary sequence. From
state 15 (HHHH) it increments to state 0 (LLLL). The clock
inputs of all flip-flops are driven in parallel through a clock
buffer. Thus all changes of the Q outputs (except due to
Master Reset of the VHC161) occur as a result of, and syn-
chronous with, the LOW-to-HIGH transition of the CP input
signal. The circuits have four fundamental modes of opera-
tion, in order of precedence: asynchronous reset, parallel
load, count-up and hold. Five control inputs—Master
Reset, Parallel Enable (PE), Count Enable Parallel (CEP)
and Count Enable Trickle (CET)—determine the mode of
operation, as shown in the Mode Select Table. A LOW sig-
nal on MR overrides all other inputs and asynchronously
forces all outputs LOW. A LOW signal on PE overrides
counting and allows information on the Parallel Data (Pn)
inputs to be loaded into the flip-flops on the next rising
edge of CP. With PE and MR HIGH, CEP and CET permit
counting when both are HIGH. Conversely, a LOW signal
on either CEP or CET inhibits counting.
The VHC161 uses D-type edge-triggered flip-flops and
changing the PE, CEP and CET inputs when the CP is in
either state does not cause errors, provided that the recom-
mended setup and hold times, with respect to the rising
edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 15. To implement synchro-
nous multistage counters, the TC outputs can be used with
the CEP and CET inputs in two different ways.
Figure 1 shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC
delay of the first stage, plus the cumulative CET to TC
delays of the intermediate stages, plus the CET to CP
setup time of the last stage. This total delay plus setup time
sets the upper limit on clock frequency. For faster clock
rates, the carry lookahead connections shown in Figure 2
are recommended. In this scheme the ripple delay through
the intermediate stages commences with the same clock
that causes the first stage to tick over from max to min to
start its final cycle. Since this final cycle requires 16 clocks
to complete, there is plenty of time for the ripple to progress
through the intermediate stages. The critical timing that lim-
its the clock period is the CP to TC delay of the first stage
plus the CEP to CP setup time of the last stage. The TC
output is subject to decoding spikes due to internal race
conditions and is therefore not recommended for use as a
clock or asynchronous reset for flip-flops, registers or
counters.
Logic Equations: Count Enable
= CEP • CET • PE
TC
= Q
0 • Q1 • Q2 • Q3 • CET
FIGURE 1. Multistage Counter with Ripple Carry
FIGURE 2. Multistage Counter with Lookahead Carry
Pin Names
Description
CEP
Count Enable Parallel Input
CET
Count Enable Trickle Input
CP
Clock Pulse Input
MR
Asynchronous Master Reset Input
P0–P3
Parallel Data Inputs
PE
Parallel Enable Inputs
Q0–Q3
Flip-Flop Outputs
TC
Terminal Count Output


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