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IRAM136-0760A2 Datasheet(PDF) 4 Page - International Rectifier

Part No. IRAM136-0760A2
Description  5A, 600V with Open Emitter Pins
Download  17 Pages
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Maker  IRF [International Rectifier]
Homepage  http://www.irf.com
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IRAM136-0760A2 Datasheet(HTML) 4 Page - International Rectifier

 
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IRAM136-0760A
Inverter Section Switching Characteristics @ TJ= 25°C
Symbol
Parameter
Min
Typ
Max
Units Conditions
EON
Turn-On Switching Loss
---
210
340
EOFF
Turn-Off Switching Loss
---
20
30
ETOT
Total Switching Loss
---
245
370
EREC
Diode Reverse Recovery energy
---
15
25
tRR
Diode Reverse Recovery time
---
135
---
ns
EON
Turn-on Switching Loss
---
300
---
EOFF
Turn-off Switching Loss
---
50
---
ETOT
Total Switching Loss
---
350
---
EREC
Diode Reverse Recovery energy
---
30
---
tRR
Diode Reverse Recovery time
---
170
---
ns
QG
Turn-On IGBT Gate Charge
---
9
13
nC
IC=4A, V
+=400V, V
CC=15V
RBSOA
Reverse Bias Safe Operating Area
TJ=150°C, IC=3.5A, VP=600V
V
+= 450V
VCC=+15V to 0V
See CT3
SCSOA
Short Circuit Safe Operating Area
5
---
---
μs
TJ=25°C, VP=600V,
V
+= 360V,
VCC=+15V to 0V
See CT2
ICSC
Short Circuit Collector Current
---
30
---
A
TJ=25°C, V
+= 400V, V
CC=15V
See CT2
IC=3.5A, V
+=400V
VCC=15V, L=1.2mH
Energy losses include "tail" and
diode reverse recovery
See CT1
IC=3.5A, V
+=400V
VCC=15V, L=1.2mH, TJ=150°C
Energy losses include "tail" and
diode reverse recovery
See CT1
μJ
μJ
FULL SQUARE
Recommended Operating Conditions Driver Function
Symbol
Definition
Min
Typ
Max
Units
VB1,2,3
High side floating supply voltage
VS+12
VS+15
VS+20
VS1,2,3
High side floating supply offset voltage
Note 4
---
450
VCC
Low side and logic fixed supply voltage
12
15
20
VITRIP
ITRIP input voltage
VSS
---
VSS+5
VIN
Logic input voltage LIN, HIN, FLT/EN
VSS
---
VSS+5
V
HIN
High side PWM pulse width
1
---
---
μs
Deadtime
External dead time between HIN and LIN
1
---
---
μs
Note 3: For more details, see IR21364 data sheet
Note 4: Logic operational for Vs from COM-5V to COM+600V. Logic state held for Vs from COM-5V to COM-VBS.
(please refer to DT97-3 for more details)
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. All voltages are absolute referenced to COM. The VS offset is tested with all supplies biased at
15V differential (Note 3)
V
V
4
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