11

NN30195A

Ver. CEB

OPERATION ( Continued )

3. Output Voltage Setting

The Output Voltage can be set by external resistance of

FB pin, and its calculation is as follows.

(VIN = 5 V, IOUT = 0 A, FCCM, Fsw = 1 MHz)

Below resistors are recommended for following popular

output voltage.

VOUT = ( 1 +

)

× 0.6

RFB1

RFB2

1.5 k

1.0 k

1.0

1.0 k

1.0 k

RFB2 [Ω]

2.0 k

1.8

4.5 k

3.3

RFB1 [Ω]

VOUT [V]

VOUT

RFB1

VFB ( 0.6 V )

RFB2

Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.

Note: RFB2 can be set to a maximum value of 10 kΩ.

A larger FBR2 value will be more susceptible

to noise.

VFB comparator threshold is adjusted to

± 1 %, but the

actual output voltage accuracy becomes more than

±

1 % due to the influence from the circuits other than VFB

comparator.

In the case of VOUT setting = 1.0 V, the actual output

voltage accuracy becomes

± 2 %.

(VIN = 5.0 V, IOUT = 0 A, FCCM, Fsw = 1 MHz).

4. Soft Start Setting

Soft Start function maintains the smooth control of the

output voltage during start up by adjusting soft start

time. When the CTL1 or CTL2 (or both) pin becomes

High, the current (2 µA) begin to charge toward the

external capacitor (Css) of SS pin, and the voltage of

SS pin increases straightly.

When Css is set at 10 nF, soft-start time is

approximately 3 ms.

Css

Time

Start

Soft

×

=

μ

2

6

.

0

(sec)

Because the voltage of FB pin is controlled by the

voltage of SS pin during start up, the voltage of FB

increase straightly to the regulation voltage (0.6 V)

together with the voltage of SS pin and keep the

regulation voltage after that. On the other hand, the

voltage of SS pin increase to about 2.8 V and keep the

voltage. The calculation of Soft Start Time is as follows.

CTL1

or

CTL2

SS

VOUT

VFB

0.6 V

Soft Start Time (s)

Figure : Soft Start Operation

UVLO

VREG

2.2 V

2.55 V

5. Power ON / OFF sequence

(1) When the CTL1/2 pin is set to “High” after the VIN

settles, UVLO is released if VIN exceeds its threshold,

then the VREG starts up.

(2) When VREG voltage exceeds its threshold, the

SOFT START sequence is enabled. The capacitor

connected to the SS pin begins to charge and the SS pin

voltage increases linearly.

(3) The VOUT pin (DCDC Output) voltage increases at

the same rate as the SS pin. Normal operation begins

after the VOUT pin reaches the set voltage.

(4) When the CTL1/2 pin is set to “Low”, VREG and

UVLO stop operation. The VOUT pin / SS pin voltage

starts to drop and the VOUT pin discharge by internal

MOSFET (R = 50 Ω).

Note: The SS pin capacitor should be discharged

completely before restarting the startup sequence. An

incomplete discharge process might result in an

overshoot of the output voltage.