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EPC1064 Datasheet(PDF) 6 Page - Altera Corporation |
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EPC1064 Datasheet(HTML) 6 Page - Altera Corporation |
6 / 26 page Page 6 Device Configuration Configuration Devices for SRAM-Based LUT Devices January 2012 Altera Corporation Device Configuration The EPC1, EPC2, and EPC1441 devices store configuration data in its erasable programmable read-only memory (EPROM) array and serially clock data out using an internal oscillator. The OE, nCS, and DCLK pins supply the control signals for the address counter and the DATA output tri-state buffer. The configuration device sends a serial bitstream of configuration data to its DATA pin, which is routed to the DATA0 input of the FPGA. The control signals for configuration devices, OE, nCS, and DCLK, interface directly with the FPGA control signals, nSTATUS, CONF_DONE, and DCLK. All Altera FPGAs can be configured by a configuration device without requiring an external intelligent controller. 1 An EPC2 device cannot configure FLEX 8000 or FLEX 6000 devices. For configuration devices that support FLEX 8000 or FLEX 6000 devices, refer to Table 2. Figure 2 shows the basic configuration interface connections between the configuration device and the Altera FPGA. The EPC2 device allows you to begin configuration of the FPGA using an additional pin, nINIT_CONF. The nINIT_CONF pin of the EPC2 device can be connected to the nCONFIG pin of the FPGA, which allows the INIT_CONF JTAG instruction to begin FPGA configuration. The INIT_CONF JTAG instruction causes the EPC2 device to drive the nINIT_CONF pin low, which in turn pulls the nCONFIG pin low. Pulling the nCONFIG pin low on the FPGA will reset the device. When the JTAG state machine exits this state, the nINIT_CONF pin is released and pulled high by an internal 1-k resistor, which in turn pulls the nCONFIG pin high to begin configuration. If you do not use the nINIT _CONF pin, disconnect the nINIT_CONF pin, and pull the nCONFIG pin of the FPGA to VCC either directly or through a resistor. Figure 2. Altera FPGA Configured Using an EPC1, EPC2, or EPC1441 Configuration Device (1) Notes to Figure 2: (1) For more information about configuration interface connections, refer to the configuration chapter in the appropriate device handbook. (2) The nINIT_CONF pin which is available on EPC2 devices has an internal pull-up resistor that is always active. This means an external pull-up resistor is not required on the nINIT_CONF/nCONFIG line. The nINIT_CONF pin does not need to be connected if its functionality is not used. If the nINIT_CONF pin is not used or unavailable, nCONFIG must be pulled to VCC either directly or through a resistor. (3) EPC2 devices have internal programmable pull-up resistors on OE and nCS pins. If internal pull-up resistors are used, do not use external pull-up resistors on these pins. The internal pull-up resistors are set by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration device option when you generate programming files. FPGA Configuration Device DCLK DATA OE (3) nCS (3) nINIT_CONF (2) MSEL DCLK DATA0 nSTATUS CONF_DONE nCONFIG VCC VCC GND nCE VCC nCEO nCASC N.C. N.C. n (2) (3) (3) |
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