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74LVX163 Datasheet(PDF) 1 Page - Fairchild Semiconductor

Part No. 74LVX163
Description  Low Voltage Synchronous Binary Counter with Synchronous Clear
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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74LVX163 Datasheet(HTML) 1 Page - Fairchild Semiconductor

   
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October 1996
Revised March 1999
© 1999 Fairchild Semiconductor Corporation
DS012157.prf
www.fairchildsemi.com
74LVX163
Low Voltage Synchronous Binary Counter with
Synchronous Clear
General Description
The LVX163 is a synchronous modulo-16 binary counter.
This device is synchronously presettable for application in
programmable dividers and has two types of Count Enable
inputs plus a Terminal Count output for versatility in forming
multistage counters. The CLK input is active on the rising
edge. Both PE and MR inputs are active on low logic lev-
els. Presetting is synchronous to rising edge of the CLK
and the Clear function of the LVX163 is synchronous to the
CLK. Two enable inputs (CEP and CET) and Carry Output
are provided to enable easy cascading of counters, which
facilitates easy implementation of n-bit counters without
using external gates.
The inputs tolerate voltages up to 7V allowing the interface
of 5V systems to 3V systems.
Features
s Input voltage level translation from 5V to 3V
s Ideal for low power/low noise 3.3V applications
s Guaranteed simultaneous switching noise and dynamic
threshold performance
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number
Package Number
Package Description
74LVX163M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
74LVX163SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX163MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin
Description
Names
CEP
Count Enable Parallel Input
CET
Count Enable Trickle Input
CP
Clock Pulse Input
MR
Synchronous Master Reset Input
P0–P3
Parallel Data Inputs
PE
Parallel Enable Inputs
Q0–Q3
Flip-Flop Outputs
TC
Terminal Count Output


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