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S29AL016J70TFI020 Datasheet(PDF) 17 Page - SPANSION

Part # S29AL016J70TFI020
Description  CMOS 3.0 Volt-only Boot Sector Flash Memory
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April 12, 2012 S29AL016J_00_12
She e t
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC
Characteristics on page 41 represents the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the system
drives the RESET# pin to VIL for at least a period of tRP, the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state machine to reading array data. The operation that was
interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure
data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS ±0.3V, the device
draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS ±0.3/0.1V, the standby
current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory. Note that the CE# pin
should only go to VIL after RESET# has gone to VIH. Keeping CE# at VIL from power up through the first read
could cause the first read to retrieve erroneous data.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the
internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not executing (RY/BY# pin is 1), the reset operation is
completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the
RESET# pin returns to VIH.
Refer to the tables in AC Characteristics on page 43 for RESET# parameters and to Figure 17.2 on page 44
for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high
impedance state.

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