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74LVX00 Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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74LVX00 Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 6 page © 2005 Fairchild Semiconductor Corporation DS011551 www.fairchildsemi.com February 1993 Revised February 2005 74LVX00 Low Voltage Quad 2-Input NAND Gate General Description The LVX00 contains four 2-input NAND gates. The inputs tolerate voltages up to 7V allowing the interface of 5V sys- tems to 3V systems. Features s Input voltage level translation from 5V to 3V s Ideal for low power/low noise 3.3V applications s Guaranteed simultaneous switching noise level and dynamic threshold performance Ordering Code: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Logic Symbol IEEE/IEC Connection Diagram Pin Descriptions Order Number Package Package Description Number 74LVX00M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVX00MX_NL (Note 1) M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVX00SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVX00MTCX_NL (Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pin Names Description An, Bn Inputs On Outputs |
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