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74LVTH543 Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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74LVTH543 Datasheet(HTML) 2 Page - Fairchild Semiconductor |
2 / 7 page ![]() www.fairchildsemi.com 2 Logic Symbols IEEE/IEC Functional Description The LVTH543 contains two sets of D-type latches, with separate input and output controls for each. For data flow from A to B, for example, the A to B Enable (CEAB) input must be LOW in order to enter data from the A Port or take data from the B Port as indicated in the Data I/O Control Table. With CEAB LOW, a low signal on (LEAB) input makes the A to B latches transparent; a subsequent LOW- to-HIGH transition of the LEAB line puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the B out- put buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA. Data I/O Control Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Note: A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA, and OEBA. Logic Diagram Please not that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Inputs Latch Status Output CEAB LEAB OEAB Buffers H X X Latched High Z X H X Latched — L L X Transparent — XX H — High Z L X L — Driving |