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74LVTH16543 Datasheet(PDF) 2 Page - Fairchild Semiconductor

Part No. 74LVTH16543
Description  Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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74LVTH16543 Datasheet(HTML) 2 Page - Fairchild Semiconductor

   
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Connection Diagram
Pin Descriptions
Functional Description
The LVT16543 and LVTH16543 contain two sets of D-type
latches, with separate input and output controls for each.
For data flow from A to B, for example, the A to B Enable
(CEAB) input must be LOW in order to enter data from the
A Port or take data from the B Port as indicated in the Data
I/ O Control Table. With CEAB LOW, a low signal on
(LEAB) input makes the A to B latches transparent; a sub-
sequent LOW-to-HIGH transition of the LEAB line puts the
A latches in the storage mode and their outputs no longer
change with the A inputs. With CEAB and OEAB both
LOW, the B output buffers are active and reflect the data
present on the output of the A latches. Control of data flow
from B to A is similar, but using the CEBA, LEBA and
OEBA. Each byte has separate control inputs, allowing the
device to be used as two 8-bit transceivers or as one 16-bit
transceiver.
Data I/O Control Table
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
A-to-B data flow shown; B-to-A flow control is the same, except using CEBAn, LEBAn and OEBAn
Pin
Names
Description
OEABn
A-to-B Output Enable Input (Active LOW)
OEBAn
B-to-A Output Enable Input (Active LOW)
CEABn
A-to-B Enable Input (Active LOW)
CEBAn
B-to-A Enable Input (Active LOW)
LEABn
A-to-B Latch Enable Input (Active LOW)
LEBAn
B-to-A Latch Enable Input (Active LOW)
A0–A15
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B0–B15
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
Inputs
Latch Status
(Byte n)
Output
Buffers
(Byte n)
CEABn
LEABn
OEABn
H
X
X
Latched
High Z
XH
X
Latched
L
L
X
Transparent
XX
H
High Z
LX
L
Driving


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