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74LVTH162374 Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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74LVTH162374 Datasheet(HTML) 2 Page - Fairchild Semiconductor |
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2 / 8 page 
www.fairchildsemi.com 2 Logic Symbol Connection Diagrams Pin Assignments for SSOP and TSSOP Pin Assignment for FBGA (Top Thru View) Pin Descriptions FBGA Pin Assignments Truth Tables H HIGH Voltage Level L LOW Voltage Level X Immaterial Z HIGH Impedance Oo Previous Oo before HIGH-to-LOW of CP Pin Names Description OEn Output Enable Input (Active LOW) CPn Clock Pulse Input I0–I15 Inputs O0–O15 3-STATE Outputs NC No Connect 1 234 56 A O0 NC OE1 CP1 NC I0 B O2 O1 NC NC I1 I2 C O4 O3 VCC VCC I3 I4 D O6 O5 GND GND I5 I6 E O8 O7 GND GND I7 I8 F O10 O9 GND GND I9 I10 G O12 O11 VCC VCC I11 I12 H O14 O13 NC NC I13 I14 J O15 NC OE2 CP2 NC I15 Inputs Outputs CP1 OE1 I0–I7 O0–O7 LH H LL L LL X Oo XH X Z Inputs Outputs CP2 OE2 I8–I15 O8–O15 LH H LL L LL X Oo XH X Z |
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