LM76

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SNIS109E – JANUARY 2000 – REVISED MARCH 2013

Logic Electrical Characteristics

Units

Symbol

Parameter

Conditions

(Limit)

V (min)

SDA and SCL Logical “1” Input

Voltage

V (max)

−0.3

V (min)

SDA and SCL Logical “0” Input

Voltage

V (max)

SDA and SCL Digital Input Hysteresis

500

250

mV (min)

2.0

V (min)

A0 and A1 Logical “1” Input Voltage

V (max)

−0.3

V (min)

A0 and A1 Logical “0” Input Voltage

0.8

V (max)

Logical “1” Input Current

0.005

1.0

μA (max)

Logical “0” Input Current

−0.005

−1.0

μA (max)

Capacitance of All Digital Inputs

20

pF

High Level Output Current

10

μA (max)

Low Level Output Voltage

0.4

V (max)

T_CRIT_A Output Saturation Voltage

(3)

0.8

V (max)

Conversions

T_CRIT_A Delay

1

(max)

Output Fall Time

250

ns (max)

(1)

(2)

Limits are ensured to AOQL (Average Outgoing Quality Level).

(3)

For best accuracy, minimize output loading. Higher sink currents can affect sensor accuracy with internal heating. This can cause an

error of 0.64°C at full rated sink current and saturation voltage based on junction-to-ambient thermal resistance.

Vdc ±10% for the LM76CHM-5, CL (load capacitance) on output lines = 80 pF unless otherwise specified. Boldface limits

Units

Symbol

Parameter

Conditions

(Limit)

SCL (Clock) Period

2.5

μs(min)

Data in Set-Up Time to SCL High

100

ns(min)

Data Out Stable after SCL Low

0

ns(min)

SDA Low Set-Up Time to SCL Low (Start Condition)

100

ns(min)

SDA High Hold Time after SCL High (Stop Condition)

100

ns(min)

(1)

(2)

Limits are ensured to AOQL (Average Outgoing Quality Level).

(3)

Timing specifications are tested at the bus input logic levels (Vin(0)=0.3xVA for a falling edge and Vin(1)=0.7xVA for a rising edge) when

the SCL and SDA edge rates are similar.

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