PA28F800B5T70 datasheet(6/44 Pages) INTEL

Part #	PA28F800B5T70

Description	5 VOLT BOOT BLOCK FLASH MEMORY

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Manufacturer	INTEL [Intel Corporation]

Direct Link	http://www.intel.com

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28F200B5, 28F004/400B5, 28F800B5

E

6

PRELIMINARY

SmartVoltage

technology

enables

fast

factory

programming and low-power designs. Specifically

designed for 5 V systems, 5 Volt Boot Block Flash

components support read operations at 5 V VCC

and internally configure to program/erase at 5 V or

12 V. The 12 V VPP option renders the fastest

program and erase performance which will increase

your factory throughput. With the 5 V VPP option,

VCC and VPP can be tied together for a simple 5 V

design. In addition, the dedicated VPP pin gives

complete data protection when VPP

≤ VPPLK.

The memory array is asymmetrically divided into

blocks

in

an

asymmetrical

architecture

to

accommodate microprocessors that boot from the

top (denoted by -T suffix) or the bottom (-B suffix)

of

the

memory

map.

The

blocks

include

a

hardware-lockable boot block (16,384 bytes), two

parameter blocks (8,192 bytes each) and main

blocks (one block of 98,304 bytes and additional

block(s) of 131,072 bytes). See Figures 4–7 for

memory maps. Each block can be independently

erased

and

programmed

100,000

times

at

commercial

temperature

or

10,000

times

at

extended temperature. At automotive temperature,

each parameter block can be independently erased

and programmed 30,000 times, and each main and

boot block 1,000 times. Unlike erase operations,

which

erase

all

locations

within

a

block

simultaneously, each byte or word in the flash

memory can be programmed independently of other

memory locations.

The

hardware-lockable

boot

block

provides

complete code security for the kernel code required

for system initialization. Locking and unlocking of

the boot block is controlled by WP# and/or RP#

(see Section 3.3 for details).

The system processor interfaces to the flash device

through a Command User Interface (CUI), using

valid

command

sequences

to

initiate

device

automation. An internal Write State Machine (WSM)

automatically executes the algorithms and timings

necessary for program and erase operations. The

Status Register (SR) indicates the status of the

WSM and whether it successfully completed the

desired program or erase operation.

The Automatic

Power

Savings

(APS)

feature

substantially reduces active current when the

device is in static mode (addresses not switching).

In APS mode, the typical ICCR current is 1 mA.

When CE# and RP# pins

are at

VCC, the

component enters a CMOS standby mode. Driving

RP# to GND enables a deep power-down mode

which significantly reduces power consumption,

provides write protection, resets the device, and

clears the status register. A reset time (tPHQV) is

required from RP# switching high until outputs are

valid. Likewise, the device has a wake time (tPHEL)

from

RP#-high

until

writes

to

the

CUI

are

recognized. See Section 4.2.

The deep power-down mode can also be used as a

device reset, allowing the flash to be reset along

with the rest of the system. For example, when the

flash memory powers-up, it automatically defaults

to the read array mode, but during a warm system

reset, where power continues uninterrupted to the

system components, the flash memory

could

remain in a non-read mode, such as erase.

Consequently, the system Reset signal should be

tied to RP# to reset the memory to normal read

mode upon activation of the Reset signal. This also

provides protection against unwanted command

writes due to invalid system bus conditions during

system reset or power-up/down sequences.

These devices are configurable at power-up for

either byte-wide or word-wide input/output using the

BYTE# pin. Please see Table 2 for a detailed

description of BYTE# operations, especially the

usage of the DQ15/A–1 pin.

These 5 Volt Boot Block Flash memory products

are available in the 44-lead PSOP (Plastic Small

Outline

Package),

which

is

ROM/EPROM-

compatible, and the 48-lead TSOP (Thin Small

Outline Package, 1.2 mm thick) as shown in

Figure 1, and 2, respectively.

2.0

PRODUCT DESCRIPTION

This

section describes

the pinout

and

block

architecture of the device family.

2.1

Pin Descriptions

The pin descriptions table details the usage of each

of the device pins.

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PA28F800B5T70 Datasheet(PDF) 6 Page - Intel Corporation

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