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74LVQ74 Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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74LVQ74 Datasheet(HTML) 2 Page - Fairchild Semiconductor |
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2 / 6 page 
Pin Descriptions Pin Names Description D 1,D2 Data Inputs CP 1,CP2 Clock Pulse Inputs C D1,CD2 Direct Clear Inputs S D1,SD2 Direct Set Inputs Q 1,Q1,Q2,Q2 Outputs Truth Table Inputs Outputs S D C D CP D Q Q LH X X HL HL X X LH LL X X H H HH N HH L HH N LL H HH L X Q 0 Q 0 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Clock Transition Q0(Q0) = Previous Q(Q) before LOW-to-HIGH Transition of Clock Logic Diagram DS011347-6 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 |
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