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H5TQ2G63BFR-12C Datasheet(PDF) 2 Page - Hynix Semiconductor |
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H5TQ2G63BFR-12C Datasheet(HTML) 2 Page - Hynix Semiconductor |
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2 / 93 page  APCPCWM_4828539:WP_0000002WP_0000002 Rev. 0.5 / Aug. 2010 2 H5TQ2G63BFR Revision History Revision No. History Page Draft Date Remark 0.1 Preliminary Initial Release Sep. 2009 Preliminary 0.2 Added Mode Register (MR0, MR1, MR2,MR3, MPR) Oct. 2009 0.3 Added IDD value(All Items) @800/9000Mhz Changed AC timing(nRCD, nRC, nRAS, nRP) @800Mhz Changed Speed Bin(CL, CWL & Min/Max timing ) @800/900Mhz, 1.0Ghz 65 56 67 ~69 Nov.2009 0.4 Corrected Typo and wording Changed Single Ended AC and DC Input Levels table Updated AC Overshoot/Undershoot Specification for 1GHz Added timings for 900MHz/1.0GHz(table1) Changed & Updated Idd Specification table Changed Speed Bin for 800/900MHz/1.0Ghz Changed Electrical Characteristics and AC Timing All 34 42 56 65 67~69 71~77 May. 2010 0.5 Changed Speed Bin for 800/900MHz 67,68 Aug. 2010 *33ed5962-ee6c* B20337/178.104.2.234/2010-08-26 09:03 |
Similar Part No. - H5TQ2G63BFR-12C |
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Similar Description - H5TQ2G63BFR-12C |
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