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STM32F405RG Datasheet(PDF) 28 Page - STMicroelectronics |
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STM32F405RG Datasheet(HTML) 28 Page - STMicroelectronics |
28 / 167 page Description STM32F405xx, STM32F407xx 28/167 Doc ID 022152 Rev 2 Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs. Note: When in Standby mode, only an RTC alarm/event or an external reset can wake up the device provided VDD is supplied by an external battery. 2.2.19 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. 2.2.20 Timers and watchdogs The STM32F405xx and STM32F407xx devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 3 compares the features of the advanced-control, general-purpose and basic timers. |
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