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74LVQ240 Datasheet(PDF) 1 Page - Fairchild Semiconductor

Part No. 74LVQ240
Description  Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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74LVQ240 Datasheet(HTML) 1 Page - Fairchild Semiconductor

   
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74LVQ240
Low Voltage Octal Buffer/Line Driver with 3-STATE
Outputs
General Description
The LVQ240 is an inverting octal buffer and line driver de-
signed to be employed as a memory address driver, clock
driver and bus oriented transmitter or receiver which pro-
vides improved PC board density.
Features
n
Ideal for low power/low noise 3.3V applications
n
Implements patented EMI reduction circuitry
n
Available in SOIC JEDEC, SOIC EIAJ, and QSOP
packages
n
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
Improved latch-up immunity
n
Guaranteed incident wave switching into 75
n
4 kV minimum ESD immunity
Ordering Code:
Order Number
Package Number
Package Description
74LVQ240SC
M20B
20-Lead (0.300" Wide) Molded Small Outline Package, SOIC, JEDEC
74LVQ240SJ
M20D
20-Lead Molded Shrink Small Outline Package, SOIC, EIAJ
74LVQ240QSC
MQA20
20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP, JEDEC
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Description
OE
1,OE2
3-STATE Output Enable Inputs
I
0–I7
Inputs
O
0–O7
Outputs
Connection Diagram
Truth Tables
Inputs
Outputs
OE
1
I
n
(Pins 12, 14, 16, 18)
LL
H
LH
L
HX
Z
Inputs
Outputs
OE
2
I
n
(Pins 3, 5, 7, 9)
LL
H
LH
L
HX
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
IEEE/IEC
DS011611-1
Pin Assignment,
SOIC and QSOP
DS011611-2
May 1998
© 1998 Fairchild Semiconductor Corporation
DS011611
www.fairchildsemi.com


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