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HS0-3530ARH-Q Datasheet(PDF) 2 Page - Intersil Corporation |
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HS0-3530ARH-Q Datasheet(HTML) 2 Page - Intersil Corporation |
2 / 2 page HS-3530ARH, HS-3530AEH 2 Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN4653.1 December 12, 2012 For additional products, see www.intersil.com/product_tree Die Characteristics DIE DIMENSIONS: 1720µm x 1390µm x 533µm ±25.4µm (68 mils x 55 mils x 21 mils ±1 mil) INTERFACE MATERIALS GLASSIVATION Type: Silox (SiO2) Thickness: 8.0kA ±1.0kA TOP METALLIZATION Type: AlSiCu Thickness: 16.0kA ±2kA SUBSTRATE: Radiation Hardened Silicon Gate, Dielectric Isolation BACKSIDE FINISH: Silicon ASSEMBLY RELATED INFORMATION SUBSTRATE POTENTIAL: Unbiased (DI) ADDITIONAL INFORMATION WORST CASE CURRENT DENSITY: <2.0 x 105 A/cm2 TRANSISTOR COUNT: 49 Metallization Mask Layout Pin Numbers shown are for the Can Package HS-3530ARH, HS-3530AEH OFFSET (1) ISET (8) NC V+ (7) NC OUTPUT (6) OFFSET (5) NC V- (4) NC IN+ (3) IN- (2) |
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