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74LCX574 Datasheet(PDF) 2 Page - Fairchild Semiconductor

Part No. 74LCX574
Description  Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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74LCX574 Datasheet(HTML) 2 Page - Fairchild Semiconductor

 
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74LCX574 Rev. 2.0.0
Logic Symbol
Connection Diagrams
Pin Assignments for
SOIC, SOP, SSOP, TSSOP
Pad Assignments for DQFN
(Top View)
Pin Descriptions
Truth Table
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
Z
= High Impedance
= LOW-to-HIGH Transition
NC
= No Change
Functional Description
The LCX574 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are com-
mon to all flip-flops. The eight flip-flops will store the state
of their individual D inputs that meet the setup and hold
time requirements on the LOW-to-HIGH Clock (CP) tran-
sition. With the Output Enable (OE) LOW, the contents of
the eight flip-flops are available at the outputs. When OE
is HIGH, the outputs go to the high impedance state.
Operation of the OE input does not affect the loading of
the flip-flops.
D0 D1 D2 D3 D4 D5 D6 D7
O0
OE
CP
O1 O2 O3 O4 O5 O6 O7
D1
D2
D3
D4
D5
D6
D7
GND
D0
O1
O2
O3
O4
O5
O6
O7
CP
O0
VCC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
D1
D2
D3
D4
D5
D6
D7
GND
D0
O1
O2
O3
O4
O5
O6
O7
CP
O0
VCC
120
2
3
4
5
6
7
8
9
10
11
19
18
17
16
15
14
13
12
OE
Pin Names
Description
D0–D7
Data Inputs
CP
Clock Pulse Input
OE
3-STATE Output Enable Input
O0–O7
3-STATE Outputs
Inputs
Internal Outputs
Function
OE CP
D
Q
On
HH
LNCZ
Hold
HH
HNCZ
Hold
HL
HZ
Load
HH
LZ
Load
LL
HL
Data Available
LH
LH
Data Available
LH
LNCNC
No Change in Data
LH
HNCNC
No Change in Data
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propaga-
tion delays.
C
O0
CP
OE
O1
O2
O3
O4
O5
O6
O7
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
CD
Q
CD
Q
CD
Q
CD
Q
CD
Q
CD
Q
CD
Q


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