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74LCX16240 Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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74LCX16240 Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 8 page © 2005 Fairchild Semiconductor Corporation DS011999 www.fairchildsemi.com February 1994 Revised May 2005 74LCX16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 5V Tolerant Inputs and Outputs General Description The LCX16240 contains sixteen inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented transmit- ter/receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The LCX16240 is designed for low voltage (2.5V or 3.3V) VCC applications with capacity of interfacing to a 5V signal environment. The LCX16240 is fabricated with an advanced CMOS tech- nology to achieve high speed operation while maintaining CMOS low power dissipation. Features s 5V tolerant inputs and outputs s 2.3V to 3.6V VCC specifications provided s 4.5 ns tPD max (VCC 3.3V), 20 PA ICC max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s r24 mA output drive (VCC 3.0V) s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human body model ! 2000V Machine model ! 200V Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Logic Symbol Pin Descriptions GTO ¥ is a trademark of Fairchild Semiconductor Corporation. Order Number Package Number Package Description 74LCX16240MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LCX16240MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Pin Names Description OEn Output Enable Inputs (Active LOW) I0–I15 Inputs O0–O15 Outputs |
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