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74F564 Datasheet(PDF) 2 Page - Fairchild Semiconductor

Part No. 74F564
Description  Octal D-Type Flip-Flop with 3-STATE Outputs
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74F564 Datasheet(HTML) 2 Page - Fairchild Semiconductor

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Unit Loading/Fan Out
Functional Description
The 74F564 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold times
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Function Table
H
= HIGH Voltage Level
Z
= High Impedance
L
= LOW Voltage Level
 = LOW-to-HIGH Transition
X
= Immaterial
NC
= No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
D0–D7
Data Inputs
1.0/1.0
20
µA/−0.6 mA
CP
Clock Pulse Input (Active Rising Edge)
1.0/1.0
20
µA/−0.6 mA
OE
3-STATE Output Enable Input (Active LOW)
1.0/1.0
20
µA/−0.6 mA
O0–O7
3-STATE Outputs
150/40 (33.3)
−3 mA/24 mA (20 mA)
Inputs
Internal Outputs
Function
OE
CP
D
Q
O
H
H
L
NC
Z
Hold
HHH
NC
Z
Hold
H

L
H
Z
Load
H

H
L
Z
Load
L

L
H
H
Data Available
L

H
L
L
Data Available
L
H
L
NC
NC
No Change in Data
L
H
H
NC
NC
No Change in Data


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