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74F545 Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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74F545 Datasheet(HTML) 2 Page - Fairchild Semiconductor |
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2 / 6 page 
www.fairchildsemi.com 2 Unit Loading/Fan Out Truth Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL OE Output Enable Input (Active LOW) 1.0/2.0 20 µA/−1.2 mA T/R Transmit/Receive Input 1.0/2.0 20 µA/−1.2 mA A0–A7 Side A 3-STATE Inputs or 3.5/1.083 70 µA/−650 µA 3-STATE Outputs 150/40 (33.3) −3 mA/24 mA (20 mA) B0–B7 Side B 3-STATE Inputs or 3.5/1.083 70 µA/−650 µA 3-STATE Outputs 600/106.6 (80) −12 mA/64 mA (48 mA) Inputs Outputs OE T/R L L Bus B Data to Bus A L H Bus A Data to Bus B HX High Z |
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