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74F403A Datasheet(PDF) 2 Page - Fairchild Semiconductor

Part No. 74F403A
Description  First-In First-Out (FIFO) Buffer Memory
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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74F403A Datasheet(HTML) 2 Page - Fairchild Semiconductor

 
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2
Unit Loading/Fan Out:
See Section 2 for U.L. definitions
Block Diagram
Functional Description
As shown in the Block Diagram the 74F403A consists of
three sections:
1. An Input register with parallel and serial data inputs as
well as control inputs and outputs for input handshak-
ing and expansion.
2. A 4-bit wide, 14-word deep fall-through stack with self-
contained control logic.
3. An Output Register with parallel and serial data outputs
as well as control inputs and outputs for output hand-
shaking and expansion.
Since these three sections operate asynchronously and
almost independently, they will be described separately
below.
INPUT REGISTER (DATA ENTRY)
The Input Register can receive data in either bit-serial or in
4-bit parallel form. It stores this data until it is sent to the
fall-through stack and generates the necessary status and
control signals.
Figure 1 is a conceptual logic diagram of the input section.
As described later, this 5-bit register is initialized by setting
the F3 flip-flop and resetting the other flip-flops. The Q out-
put of the last flip-flop (FC) is brought out as the “Input
Register Full” output (IRF). After initialization this output is
HIGH.
Parallel Entry— A HIGH on the PL input loads the D0-D3
inputs into the F0-F3 flip-flops and sets the FC flip-flop. This
forces the IRF output LOW indicating that the input register
is full. During parallel entry, the CPSI input must be LOW. If
parallel expansion is not being implemented, IES must be
LOW to establish row mastership (see Expansion section).
Serial Entry— Data on the DS input is serially entered into
the F3, F2, F1, F0, FC shift register on each HIGH-to-LOW
transition of the CPSI clock input, provided IES and PL are
LOW.
After the fourth clock transition, the four data bits are
located in the four flip-flops, F0-F3. The FC flip-flop is set,
forcing the IRF output LOW and internally inhibiting CPSI
clock pulses from affecting the register, Figure 2 illustrates
the final positions in a 74F403A resulting from a 64-bit
serial bit train. B0 is the first bit, B63 the last bit.
Pin
Description
U.L.
Input IIH/IIL
Names
HIGH/LOW Output IOH/IOL
D0 D3 Parallel Data Inputs
1.0/0.667
20
µA/400 µA
DS
Serial Data Input
1.0/0.667
20
µA/400 µA
PL
Parallel Load Input
1.0/0.667
20
µA/400 µA
CPSI
Serial Input Clock
1.0/0.667
20
µA/400 µA
IES
Serial Input Enable
1.0/0.667
20
µA/400 µA
TTS
Transfer to Stack Input
1.0/0.667
20
µA/400 µA
OES
Serial Output Enable
1.0/0.667
20
µA/400 µA
TOS
Transfer Out Serial
1.0/0.667
20
µA/400 µA
TOP
Transfer Out Parallel
1.0/0.667
20
µA/400 µA
MR
Master Reset
1.0/0.667
20
µA/400 µA
OE
Output Enable
1.0/0.667
20
µA/400 µA
CPSO
Serial Output Clock
1.0/0.667
20
µA/400 µA
Q0 Q3 Parallel Data Outputs
285/26.7
5.7 mA/16 mA
QS
Serial Data Output
285/26.7
5.7 mA/16 mA
IRF
Input Register Full
20/13.3
400 µA/8 mA
ORE
Output Register Empty
20/13.3
400 µA/8 mA


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