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74F403A Datasheet(PDF) 3 Page - Fairchild Semiconductor

Part No. 74F403A
Description  First-In First-Out (FIFO) Buffer Memory
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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74F403A Datasheet(HTML) 3 Page - Fairchild Semiconductor

 
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FIGURE 1. Conceptual Input Section
FIGURE 2. Final Positions in a 74F403A
Resulting from a 64-Bit Serial Train
Transfer to the Stack— The outputs of Flip-Flops F0-F3
feed the stack. A LOW level on the TTS input initiates a
“fall-through” action. If the top location of the stack is
empty, data is loaded into the stack and the input register is
re-initialized. Note that this initialization is postponed until
PL is LOW again. Thus, automatic FIFO action is achieved
by connecting the IRF output to the TTS input.
An RS Flip-Flop (the Request Initialization Flip-Flop shown
in Figure 10) in the control section records the fact that
data has been transferred to the stack. This prevents multi-
ple entry of the same word into the stack despite the fact
the IRF and TTS may still be LOW. The Request Initializa-
tion Flip-Flop is not cleared until PL goes LOW. Once in the
stack, data falls through the stack automatically, pausing
only when it is necessary to wait for an empty next location.
In the 74F403A as in most modern FIFO designs, the MR
input only initializes the stack control section and does not
clear the data.
OUTPUT REGISTER (DATA EXTRACTION)
The Output Register receives 4-bit data words from the
bottom stack location, stores it and outputs data on a 3-
STATE 4-bit parallel data bus or on a 3-STATE serial data
bus. The output section generates and receives the neces-
sary status and control signals. Figure 3 is a conceptual
logic diagram of the output section.


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