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74F377SC Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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74F377SC Datasheet(HTML) 2 Page - Fairchild Semiconductor |
2 / 6 page www.fairchildsemi.com 2 Unit Loading/Fan Out Mode Select-Function Table H = HIGH Voltage Level h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition L = LOW Voltage Level I = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition X = Immaterial = LOW-to-HIGH Clock Transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL D0–D7 Data Inputs 1.0/1.0 20 µA/−0.6 mA CE Clock Enable (Active LOW) 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input 1.0/1.0 20 µA/−0.6 mA Q0–Q7 Data Outputs 50/33.3 −1 mA/20 mA Operating Mode Inputs Output CP CE Dn Qn Load “1” Ih H Load “0” II L Hold h X No Change (Do Nothing) X H X No Change |
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