Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

74F299 Datasheet(PDF) 2 Page - Fairchild Semiconductor

Part No. 74F299
Description  Octal Universal Shift/Storage Register with Common Parallel I/O Pins
Download  6 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
Logo 

74F299 Datasheet(HTML) 2 Page - Fairchild Semiconductor

   
Zoom Inzoom in Zoom Outzoom out
 2 / 6 page
background image
www.fairchildsemi.com
2
Unit Loading/Fan Out
Functional Description
The 74F299 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
shift left, shift right, parallel load and hold operations. The
type of operation is determined by S0 and S1, as shown in
the Mode Select Table. All flip-flop outputs are brought out
through 3-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q0 and Q7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops. All other state changes are initi-
ated by the rising edge of the clock. Inputs can change
when the clock is in either state provided only that the rec-
ommended setup and hold times, relative to the rising edge
of CP, are observed.
A HIGH signal on either OE1 or OE2 disables the 3-STATE
buffers and puts the I/O pins in the high impedance state.
In this condition the shift, hold, load and reset operations
can still occur. The 3-STATE outputs are also disabled by
HIGH signals on both S0 and S1 in preparation for a paral-
lel load operation.
Mode Select Table
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
 = LOW-to-HIGH Clock Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
CP
Clock Pulse Input (Active Rising Edge)
1.0/1.0
20
µA/−0.6 mA
DS0
Serial Data Input for Right Shift
1.0/1.0
20
µA/−0.6 mA
DS7
Serial Data Input for Left Shift
1.0/1.0
20
µA/−0.6 mA
S0, S1
Mode Select Inputs
1.0/2.0
20
µA/−1.2 mA
MR
Asynchronous Master Reset Input (Active LOW)
1.0/1.0
20
µA/−0.6 mA
OE1, OE2
3-STATE Output Enable Inputs (Active LOW)
1.0/1.0
20
µA/−0.6 mA
I/O0–I/O7
Parallel Data Inputs or
3.5/1.083
70
µA/−0.65 mA
3-STATE Parallel Outputs
150/40(33.3)
−3 mA/24 mA (20 mA)
Q0, Q7
Serial Outputs
50/33.3
−1 mA/20 mA
Inputs
Response
MR S1 S0 CP
L
X
X
X
Asynchronous Reset; Q0–Q7 = LOW
HH
H
 Parallel Load; I/On → Qn
HL
H
 Shift Right; DS0 → Q0, Q0 → Q1, etc.
HH
L
 Shift Left; DS7 → Q7, Q7 → Q6, etc.
H
L
L
X
Hold


Html Pages

1  2  3  4  5  6 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn