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74F190 Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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74F190 Datasheet(HTML) 2 Page - Fairchild Semiconductor |
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2 / 7 page 
www.fairchildsemi.com 2 Unit Loading/Fan Out Functional Description The 74F190 is a synchronous up/down BCD decade counter containing four edge-triggered flip-flops, with inter- nal gating and steering logic to provide individual preset, count-up and count-down operations. It has an asynchro- nous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load (PL) input is LOW, information present on the Parallel Data inputs (P0–P3) is loaded into the counter and appears on the Q outputs. This operation overrides the counting func- tions, as indicated in the Mode Select Table. A HIGH signal on the CE input inhibits counting. When CE is LOW, inter- nal state changes are initiated synchronously by the LOW- to-HIGH transition of the clock input. The direction of count- ing is determined by the U/D input signal, as indicated in the Mode Select Table, CE and U/D can be changed with the clock in either state, provided only that the recom- mended setup and hold times are observed. Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches 9 in the count-up mode. The TC output will then remain HIGH until a state change occurs, whether by counting or presetting or until U/D is changed. The TC output should not be used as a clock sig- nal because it is subject to decoding spikes. The TC signal is also used internally to enable the Ripple Clock (RC) out- put. The RC output is normally HIGH. When CE is LOW and TC is HIGH, the RC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multi- stage counters. For a discussion and illustrations of the various methods of implementing multistage counters, please see the 74F191 data sheet. RC Truth Table Mode Select Table *TC is generated internally H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition
= LOW Pulse Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL CE Count Enable Input (Active LOW) 1.0/3.0 20 µA/−1.8 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA P0–P3 Parallel Data Inputs 1.0/1.0 20 µA/−0.6 mA PL Asynchronous Parallel Load Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA U/D Up/Down Count Control Input 1.0/1.0 20 µA/−0.6 mA Q0–Q3 Flip-Flop Outputs 50/33.3 −1 mA/20 mA RC Ripple Clock Output (Active LOW) 50/33.3 −1 mA/20 mA TC Terminal Count Output (Active HIGH) 50/33.3 −1 mA/20 mA Inputs Output CE TC* CP RC LH HX X H XL X H Inputs Mode PL CE U/D CP HL L Count Up HL H Count Down L X X X Preset (Asyn.) H H X X No Change (Hold) |
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