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74F174 Datasheet(PDF) 2 Page - Fairchild Semiconductor

Part No. 74F174
Description  Hex D-Type Flip-Flop with Master Reset
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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74F174 Datasheet(HTML) 2 Page - Fairchild Semiconductor

   
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Functional Description
The 74F174 consists of six edge-triggered D-type flip-flops
with individual D inputs and Q outputs. The Clock (CP) and
Master Reset (MR) are common to all flip-flops. Each D
input’s state is transferred to the corresponding flip-flop’s
output following the LOW-to-HIGH Clock (CP) transition. A
LOW input to the Master Reset (MR) will force all outputs
LOW independent of Clock or Data inputs. The 74F174 is
useful for applications where the true output only is
required and the Clock and Master Reset are common to
all storage elements.
Truth Table
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
 = LOW-to-HIGH Clock Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
D0–D5
Data Inputs
1.0/1.0
20
µA/−0.6 mA
CP
Clock Pulse Input (Active Rising Edge)
1.0/1.0
20
µA/−0.6 mA
MR
Master Reset Input (Active LOW)
1.0/1.0
20
µA/−0.6 mA
Q0–Q5
Outputs
50/33.3
−1 mA/20 mA
Inputs
Outputs
MR
CP
Dn
Qn
LX
X
L
H

HH
H

LL


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