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74ACTQ14 Datasheet(PDF) 1 Page - Fairchild Semiconductor

Part No. 74ACTQ14
Description  Quiet Series Hex Inverter with Schmitt Trigger Input
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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© 2005 Fairchild Semiconductor Corporation
DS010911
www.fairchildsemi.com
March 1991
Revised February 2005
74ACTQ14
Quiet Series
¥ Hex Inverter with Schmitt Trigger Input
General Description
The ACTQ14 contains six inverter gates each with a
Schmitt trigger input. They are capable of transforming
slowly changing input signals into sharply defined, jitter-
free output signals. In addition, they have a greater noise
margin than conventional inverters.
The ACTQ14 utilizes Fairchild Quiet Series
¥ Technology
to guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Series
¥ features
GTO
¥ output control and undershoot corrector in addition
to a split ground bus for superior performance.
The ACTQ14 has hysteresis between the positive-going
and negative-going input thresholds (typically 1.0V) which
is determined internally by transistor ratios and is essen-
tially insensitive to temperature and supply voltage varia-
tions.
Features
s ICC reduced by 50%
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Improved latch-up immunity
s Guaranteed pin-to-pin skew AC performance
s Outputs source/sink 24 mA
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Pin Descriptions
Connection Diagram
Function Table
Quiet Series
¥, FACT Quiet Series¥ and GTO¥ are trademarks of Fairchild Semiconductor Corporation.
Order Number
Package Number
Package Description
74ACTQ14SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74ACTQ14MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACTQ14PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pin Names
Description
In
Inputs
On
Outputs
Input
Output
AO
LH
HL




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