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54AC164245 Datasheet(PDF) 11 Page - STMicroelectronics

Part No. 54AC164245
Description  Rad-hard 16-bit transceiver, 3.3 V to 5 V bidirectional level shifter
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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54AC164245 Datasheet(HTML) 11 Page - STMicroelectronics

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54AC164245
Electrical characteristics
Doc ID 18093 Rev 2
11/22
PD
(3) (5)
(6)
Power dissipation, port A,
CL = 50 pF per switching output
3.3 V
VDD1 = 4.5 to 5.5 V
VDD2 = 2.7 to 3.6 V
1.5
mW/
MHz
5 V
VDD1 = 4.5 to 5.5 V
VDD2 = 4.5 to 5.5 V
2.0
Power dissipation, port B,
CL = 50 pF per switching output
3.3 V
VDD1 = 2.7 to 3.3 V
VDD2 = 2.7 to 3.6 V
1.5
5 V
VDD1 = 4.5 to 5.5 V
VDD2 = 2.7 to 3.6 V
2.0
IDDQ
Quiescent supply current port
A, VI = VDD2 or VSS
5 V
VDD1 = 5.5 V
VDD2 = 5.5 V
at 25°C
10
µA
VDD1 = 5.5 V
VDD2 = 5.5 V
at -55 to +125°C
100
Quiescent supply current port
B, VI = VDD1 or VSS
5 V
VDD1 = 5.5 V
VDD2 = 5.5 V
at 25°C
10
VDD1 = 5.5 V
VDD2 = 5.5 V
at -55 to +125°C
100
CI
Input capacitance
f = 1 MHz VDD1 = VDD2 = 0
V
15
pF
CO
Output capacitance
f = 1 MHz VDD1 = VDD2 = 0
V
15
pF
(7)
Functional test VIH = 0.7 VDD,
VIL = 0.3 VDD
VDD1 = 4.5 to 5.5 V
VDD2 = 2.7 to 3.6 V
L
H
1.
Each input/output, as applicable, is tested at the specified temperature, for the specified limits, to the tests specified in
SMD5962-98580 table I. Non-designated output terminals are high level logic, low level logic or open, except for all IDD
tests, where the output terminals are open. When performing these tests, the current meter must be placed in the circuit
such that all current flows through the meter.
2.
This device requires both VDD1 and VDD2 power supplies for operation. The power supply is indicated and followed by the
voltage to which the power supply is set to the given test.
3.
This parameter is supplied as a design limit but not guaranteed or tested.
4.
No more than one output should be shorted at a time for a maximum duration of one second.
5.
Power does not include power contribution of any CMOS output sink current.
6.
Power dissipation specified per switching output.
7.
Tests must be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic
patterns used for fault detection. The test vectors used to verify the truth table must, at minimum, test all the functions of
each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the
function table, Table 2. Functional tests are performed in sequence as approved by the qualifying activity on qualified
devices. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions:
VIH = VIH(min + 20%, -0%); VIL = VIL(max + 0%, -50%), as specified herein, for TTL, CMOS, or Schmitt compatible inputs.
Devices are guaranteed to VIH(min) and VIL(max).
Table 6.
DC specifications (1) (continued)
Symbol
Parameter
Port
voltage
Test condition (VDD)
(2)
Limits
Unit
Min.
Max.


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